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24 - bit, 250 ksps sigma - delta adc with 20 s settling data sheet ad7176 - 2 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or paten t rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2012 analog devices, inc. all rights reserved. technical support www.analog.com features fast and flexible output rate 5 sp s to 250 ksp s fast settling time 20 s channel scan data rate of 50 k sp s /channel performance specifications 17 noise free bits at 250 k sp s 20 noise free bits at 2.5 k sp s 22 noise free bits at 5 sp s inl 2.5 ppm of fsr 8 5 db r ejection of 50 hz and 60 hz with 50 ms settling user - configurable input channels 2 full y differential or 4 pseudo differential crosspoint multiplexer on - chip 2.5 v reference ( drift 2 ppm/c) internal oscillator, external crystal, or external clock po wer supply single supply: 5 v avdd 1 , 2 v to 5 v avdd2 and iovdd optional s plit supply : avdd1 and avss 2.5 v current: 7 .8 ma temperature range : ? 40c to + 105c 3 - or 4 - wire serial digital interface (schmitt trigger on sclk) crc error checking spi, qspi, microwire , and dsp compatible applications process control : plc/dcs modules temperature and pressure measurement medical and scientific multichannel instrumentation chromatography general description the ad7176 - 2 is a fast settling , highly accurate , high resolution , multiplexed - analog - to - digital converter (adc) for low band - width input signals . its inputs can be configured as two fully differential or four pseudo differential inputs via the integrated crosspoint multiplexer . an integrated precision, 2.5 v, low drift (2 ppm/c), band gap internal r eference (with an output reference buffer) adds functionality and re duces the external component count. the max imum channel scan data rate is 50 k sps ( with a settling time of 20 s ) , resulting in fully settled data of 17 noise free bits . u ser - selectable output data rates range from 5 sps to 250 k sps . the resolution increases at lower speeds. the ad7176 - 2 offers three key digital filter s . the fast settling filter maximizes the channel scan rate. the sinc3 filter maximi z es the resolution for single - channel , low speed applic ations . for 50 hz and 60 hz environments, the ad7176 - 2 specific filter minimize s the settling times or maximizes the rejection of the line frequency . t hese enhanced filter s enable simultaneous 50 hz and 60 hz rejec - tion with a 27 sps output data rate ( with a settling time of 36 ms) . system offset and gain errors can be corrected on a per channel basis . this per channel configurability extends to the type of filter and outpu t data rate used for each channel. all switching of the cross point multiplexer is controlled by the adc and can be con - figured to automatically control an external multiplexer via the gpio pins. the specifie d operating temperature range is ? 40c to +105c . the ad7176 - 2 is housed in a 24 - lead tssop package . functional block dia gram figure 1. avdd1 avss gpio0 gpio1 xtal1 clkio/xtal2 dgnd ref? ref+ refout avdd2 regcapa ain0 ain1 ain2 ain3 ain4 - adc 1.8v ldo 1.8v ldo int ref crosspoint multiplexer iovdd regcapd i/o control serial interface and control digital filter AD7176-2 buffered precision reference xtal and internal clock oscillator circuitry cs sclk din dout/rdy sync/error 1 1037-001
ad7176- 2 data sheet rev. 0 | page 2 of 68 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 3 specifications ..................................................................................... 4 timing characteristics ................................................................ 7 timing diagrams .......................................................................... 7 absolute maximum ratings ............................................................ 8 thermal resistance ...................................................................... 8 esd caution .................................................................................. 8 pin configuration and function descriptions ............................. 9 typical performance characteristics ........................................... 11 noise performance and resolution .............................................. 15 getting started ................................................................................ 1 6 power suppli es ............................................................................ 17 digital communication ............................................................. 17 configuration overview ........................................................... 19 circuit description ......................................................................... 23 analog input ............................................................................... 23 driver amplifiers ....................................................................... 23 ad7176 - 2 reference ................................................................... 26 ad7176 - 2 clock source ............................................................. 27 digita l filters ................................................................................... 28 sinc5 + sinc1 filter ..................................................................... 28 sinc3 filter ................................................................................... 29 single cycle settling ................................................................... 29 enhanced 50 hz and 60 hz rejection filters ......................... 31 operating mo des ............................................................................ 34 continuous conversion mode ................................................. 34 continuous read mode ............................................................. 35 single c onversion mode ........................................................... 36 standby and power - down modes ............................................ 37 calibration modes ...................................................................... 37 digital interface .............................................................................. 38 checksum p rotection ................................................................. 38 crc calculation ......................................................................... 39 general - purpose i/o ................................................................. 41 16- bit/24 - bit conversions ......................................................... 41 serial interface reset (dout_reset) .................................. 41 synchronization ( sync / error ) ........................................... 41 error flags ................................................................................... 42 data_stat ............................................................................... 42 iostrength ........................................................................... 42 grounding and layout .................................................................. 43 register summary .......................................................................... 44 register det ails ............................................................................... 46 communications register ......................................................... 46 status register ............................................................................. 47 adc mode register ................................................................... 48 interface mode register ............................................................ 49 regi ster check ............................................................................ 50 data register ............................................................................... 50 gpio configuration register ................................................... 51 id register ................................................................................... 52 channel map register 0 ............................................................ 53 channel map register 1 ............................................................ 54 channel map register 2 ............................................................ 55 channel map register 3 ............................................................ 56 setup configuration register 0 ................................................ 57 setup configuration register 1 ................................................ 57 setup configuration register 2 ................................................ 58 setup configuration register 3 ................................................ 58 filter configuration register 0 ................................................. 59 filter configuration register 1 ................................................. 60 filter configuration register 2 ................................................. 61 filter configuration register 3 ................................................. 62 offset register 0 ......................................................................... 63 offset reg ister 1 ......................................................................... 63 offset register 2 ......................................................................... 63 offset register 3 ......................................................................... 63 gain regis ter 0 ............................................................................ 64 gain register 1 ............................................................................ 64 gain register 2 ............................................................................ 64 gain register 3 ............................................................................ 64 outline dimensions ....................................................................... 65 ordering guide .......................................................................... 65
data sheet ad7176- 2 rev. 0 | page 3 of 68 revision history 11/ 12 revision 0 initial version
ad7176- 2 data sheet rev. 0 | page 4 of 68 specifications a vdd1 = 4.5 v to 5 .5 v, a vdd2 = 2 v to 5.5 v , iovdd = 2 v t o 5.5 v , a vss = d gnd = 0 v , ref + = 2. 5 v , ref ? = a vss , internal master clock = 16 mhz , t a = t min to t max , unless otherwise noted. table 1 . parameter test conditions/comment s min typ max unit adc speed and performance output data rate (odr) 5 250,000 sps no missing codes 1 24 bits resolution see table 6 noise see table 6 noise free resolution 250 ksps, ref+ = 5 v 17 bits 2.5 ksps, ref+ = 5 v 20 bits 5 sps, ref+ = 5 v 2 2 bits accuracy integral nonlinearity (inl) 2.5 v reference 2.5 7 ppm of fsr 5 v reference 7 ppm of fsr offset error 2 40 v offset drift 110 nv/c offset drift vs . time 3 4 5 0 nv/ 500 h ou rs gain error 2 25c 10 50 ppm/fsr gain drift vs. temperature 1 0.5 1 ppm/ fsr/ c gain drift vs . time 3 3 ppm/ fsr/ 500 hours rejection power supply rejection avdd1, avdd2 v in = 1 v 9 0 db common - mode rejection at dc v in = 0. 1 v 95 db at 50 hz and 60 hz 1 20 sps odr (post filter) (50 hz 1 hz and 60 hz 1 hz) 1 30 db normal mode rejection 1 50 hz 1 hz and 60 hz 1 hz internal clock , 20 sps odr (post filter) 71 90 db external clock , 20 sps odr (post filter) 85 90 db analog inputs differential input voltage range v ref v absolute ain voltage limits 1 avss ? 0.050 avdd1 + 0.05 v analog input current input current 48 a/v input current drift external clock 0.75 na/v/c internal clock (2 .5 % clock) 4 na/v/c crosstalk 1 khz input ?1 20 db internal reference 100 nf external capacitor on refout to avss output voltage refout with respect to avss 2.5 v initial accuracy 1 t a = 25c ? 0.16 % + 0.16 % v temperature coefficient 0c to + 105c 2 5 ppm/c ?40c to +105c 3 10 ppm/c reference load current , i load i l ?10 +10 ma power supply rejection (line regulation) avdd1 and avdd2 9 3 db load regulation ?v out /?i l 32 ppm /ma voltage noise e n , 0.1 hz to 10 hz 4.5 v rms voltage noise density e n , 1 khz 215 nv/hz
data sheet ad7176- 2 rev. 0 | page 5 of 68 parameter test conditions/comment s min typ max unit turn - on settling time 100 nf capacitor 60 s long - term stability 3 50 0 hours 460 ppm short circuit i sc 25 ma external reference reference input voltage reference input = (ref+) C (ref?) 1 2.5 avdd1 v absolute reference input voltage limits 1 avss ? 0.05 avdd1 + 0.05 v average reference input current 72 a/v average reference input current drift external clock 1.2 na/v/c internal clock 6 na/v/c normal mode rejection 1 see the rejection parameter section of this table common - mode rejection 83 db general - purpose i/o (gpio 0, gpio 1) w ith respect to avss output high voltage, v oh 1 i source = 200 a avss + 4 v output low voltage, v ol 1 i sink = 800 a avss + 0.4 v input mode leakage current 1 ?10 +10 a floating - state output capacitance 5 pf input high voltage, v ih 1 avss + 3 v input low voltage, v il 1 avss + 0.7 v clock internal clock frequency 16 mhz accuracy ? 2 .5 + 2 .5 % duty cycle 50:50 % output low voltage, v ol 0.4 v output high voltage, v oh 0.8 iovdd v crystal frequency 14 16 16.384 mhz start - up time 50 s external clock (clkio) 16 16.384 mhz duty cycle 1 typical duty cycle 50:50 (max:min) 30 50:50 70 % logic inputs input high voltage, v inh 1 2 v iovdd 2.3 v 0.65 iovdd v 2.3 v iovdd 5.5 v 0.7 iovdd v input low voltage, v inl 1 2 v iovdd 2.3 v 0.35 iovdd v 2.3 v iovdd 5.5 v 0.7 v hysteresis 1 iovdd > 2.7 v 0.08 0.25 v iovdd < 2.7 v 0.04 0.2 v leakage currents ?10 +10 a logic output (dout/ rdy ) output high voltage, v oh 1 iovdd 4.5 v, i source = 1 ma 0.8 iovdd v 2.7 v iovdd < 4.5 v, i source = 500 a 0.8 iovdd v iovdd < 2.7 v, i source = 200 a 0.8 iovdd v output low voltage, v ol 1 iovdd 4.5 v, i sink = 2 ma 0.4 v 2.7 v iovdd < 4.5 v, i sink = 1 ma 0.4 v iovdd < 2.7 v, i sink = 400 a 0.4 v leakage current floating state ?10 +10 a output capacitance floating state 10 pf
ad7176- 2 data sheet rev. 0 | page 6 of 68 parameter test conditions/comment s min typ max unit system calibration 1 full - scale calibration limit 1.05 fs v zero - scale calibration limit ?1.05 fs v input span 0.8 fs 2.1 fs v power requirements power supply voltage avdd1 ? avss 4.5 5.5 v avdd2 C avss 2 5.5 v avss C dgnd ?2.75 0 v iovdd ? dgnd 2 5.5 v iovdd C avss for avss < dgnd 6.35 v power supply currents all outputs unloaded , digital inputs connected to iovdd or dgnd full operating mode avdd1 current external reference 1.5 1.75 ma internal reference 1.75 2.1 ma avdd2 current external reference 4.3 4.9 ma internal reference 4.5 5.1 ma iovdd current external clock 2 2.3 ma internal clock 2.2 5 2.6 ma external crystal 2.5 ma standby mode standby (ldo on) internal reference off, total current consumption 2 2 a internal reference on, total current consumption 415 a power - down mode full power - down, ldo, internal reference 0.5 10 a power dissipation full operating mode avdd2 = 2 v, iovdd = 2 v, external clock and reference 20.1 23.15 mw avdd2 = 5 v, iovdd = 5 v, external clock and reference 39 44.75 mw avdd2 = 2 v, iovdd = 2 v, internal clock and reference 22.25 2 5.9 mw avdd2 = 5 v, iovdd = 5 v, interna l clock and reference 42.5 49 mw standby mode internal reference off, all supplies = 5 v 1 10 w internal reference on, all supplies = 5 v 2. 1 mw power - down mode full power - down 2.5 50 w 1 specification is not production tested but is supported by characterization data at the initial product release . 2 following a system or internal zero - scale calibration, the offset error is in the order of the noise for the programmed output data rate selected. a system full - scale calibration reduces the gain error to the order of the noise for the programmed output data rate. 3 the long - term stability specification is noncumulative.
data sheet ad7176- 2 rev. 0 | page 7 of 68 timing characteristi cs iovdd = 2 v to 5.5 v, dgnd = 0 v, input logic 0 = 0 v, input logic 1 = iovdd , c load = 2 0 pf , unless otherwise noted . table 2 . parameter limit at t min , t max (b version) unit test conditions/comments 1 , 2 t 3 25 ns min sclk high pulse width t 4 25 ns min sclk low pulse width read operation t 1 0 ns min cs falling edge to dout/ rdy active time 15 ns max iovdd = 4.5 v to 5.5 v 4 0 ns max iovdd = 2 v to 3.6 v t 2 3 0 ns min sclk active edge to data valid delay 4 12 ns max iovdd = 4.5 v to 5.5 v 2 5 ns max iovdd = 2 v to 3.6 v t 5 5 2.5 ns min bus relinquish time after cs inactive edge 20 ns max t 6 0 ns min sclk inactive edge to cs inactive edge t 7 10 ns min sclk inactive edge to dout/ rdy high/low write operation t 8 0 ns min cs falling edge to sclk active edge setup time 4 t 9 8 ns min data valid to sclk edge setup time t 10 8 ns min data valid to sclk edge hold time t 11 5 ns min cs rising edge to sclk edge hold time 1 sample tested during initia l release to ensure compliance. 2 see figure 2 and figure 3 . 3 the time required for the output to cross the v ol or v oh limits. 4 the sclk active edge is the falling edge of sclk. 5 rdy returns high after a read of the data register. in single conversion mode and continuous conversion mode, the same data can b e read again, if required, while rdy is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. if the c ontinuous read feature is enabled, the digital word can be read only once. timing diagrams figure 2 . read cycle timing diagram figure 3 . write cycle timing diagram t 2 t 3 t 4 t 1 t 6 t 5 t 7 cs (i) dout/rdy (o) sclk (i) i = input, o = output msb lsb 1 1037-002 i = input, o = output cs (i) sclk (i) din (i) msb lsb t 8 t 9 t 10 t 11 1 1037-003
ad7176- 2 data sheet rev. 0 | page 8 of 68 absolute maximum rat ings t a = 25c, unless otherwise noted. table 3 . parameter rating avdd1, avdd2 to avss ? 0.3 v to +6.5 v avdd1 to dgnd ? 0.3 v to +6.5 v iovdd to dgnd ? 0.3 v to +6.5 v iovdd to avss ? 0.3 v to +7.5 v avss to dgnd ? 3.25 v to +0.3 v analog input voltage to avss ? 0.3 v to avdd1 + 0.3 v reference input voltage to avss ? 0.3 v to avdd1 + 0.3 v digital input voltage to dgnd ? 0.3 v to iovdd + 0.3 v digital output voltage to dgnd ? 0.3 v to iovdd + 0.3 v ain [4:0] or digital input current 10 ma operating temperature range ? 40c to +105c storage temperature range ? 65c to +150c maximum junction temperature 150c lead soldering, reflow temperature 260c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for a device soldered on a jedec test board for surface - mount package s. the values listed in table 4 are based on simulated data. table 4 . thermal resistance package type ja unit 24- lead tssop jedec board layer 1 156 c/w jedec board layer 2 87 c/w esd caution
data sheet ad7176- 2 rev. 0 | page 9 of 68 pin configuration an d function descripti ons figure 4 . pin configuration table 5 . pin function descriptions pin no. mnemonic description 1 ain4 analog input 4. selectable through crosspoint multiplexer . 2 ref ? reference input negative terminal. ref ? can span from avss to avdd1 ? 1 v. 3 ref+ reference input positive terminal . an external reference can be applied between ref+ and ref?. ref+ can span from avdd1 to avss + 1 v. t he part functions with a reference from 1 v to avdd1. 4 refout buffered output of internal reference . the output is 2.5 v with respect to avss . 5 regcap a analog ldo regulator output . d ecoupl e this pin to avss using a 1 f cap acitor . 6 avss negative analog supply . this supply ranges from 0 v to ? 2.75 v and is n ominally set to 0 v. 7 avdd1 analog supply voltage 1 . th is voltage is 5 v 10% with respect to avss . 8 avdd2 analog supply voltage 2 . th is voltage ranges from 2 v to avdd1 with respect to avss. 9 x tal1 input 1 for crystal . 10 clkio/xtal2 clock input or output ( based on the cl oc ksel bits in the adcmode register )/ input 2 for crystal . there are four options available: internal oscillator no output. internal oscillator output to clkio/xtal2. operates at iovdd logic level. external clock input to clkio/xtal2. input should be at iovdd logic level. external crystal connected between xtal1 and clkio/xtal2. 11 dout/ rdy serial data output/data ready output. dout/ rdy serves a dual purpose. it functions as a serial data output pin to access the output shift register of the adc. the output shift register can contain data from any of the on - chip data or control register s. the data - word/control word information is placed on the dout/ rdy pin on the sclk falling edge and is valid on the sclk rising edge. when cs is high, the dout/ rdy output is tristated . when cs is low , dout/ rdy operates as a data ready pin, going low to indicate the completion of a conversion. if the data is not read after the conversion, the pin goes high before the next update occurs. the dout/ rdy falling edge can be used as an interrupt to a processor, indicating that valid data is available. 12 din serial data input to the input shift register on the adc. data in this shift register is transferred to the control registers in the adc, with the re gister address (ra) bits of the communications register identifying the appropriate register. data is clocked in on the rising edge of sclk. 13 sclk serial clock input. this serial clock input is for data transfers to and from the adc. the sclk has a schm itt - triggered input, making the interface suitable for opto - isolated applications. 14 cs chip select input. this is an active low logic input used to select the adc. cs can be used to select the adc in systems with more than one device on the serial bu s. cs can be hardwired low, allowing the adc to operate in 3 - wire mode with sclk, din, and dout used to interface with the device. when cs is high , the dout/ rdy outp ut is tristated. 1 2 3 4 5 6 7 8 9 10 12 1 1 ref? ref+ refout a vdd1 a vss regca p a ain4 a vdd2 xt al1 din dout/rd y clkio/x t al2 20 21 22 23 24 19 18 17 16 15 14 13 ain2 ain1 ain0 regcapd gpio0 gpio1 dgnd iovdd sclk cs sync/error ain3 AD7176-2 t op view (not to scale) 1 1037-004
ad7176- 2 data sheet rev. 0 | page 10 of 68 pin no. mnemonic description 15 sync / error can be switched between a logic input and a logic output in the gp iocon register . when synchronization input is enabled , this pin allows for synchronization of the digital filters and anal og modulators when using multiple ad7176 - 2 devices. when synchronization input is disabled , this pin can be used in one of three modes: active low error input mode: this mode sets the adc_error bit in the status register. active low, open - drain error output mode: the status register error bits are mapped to the error pin. the error pins of multiple devices can be wired together to a common pull - up resistor so that an error on any device can be observed. general - purpose output mode: the status of the pin is controlled by the err _ dat bit in the gp iocon register. the pin is referenced between iovdd and dgnd, as opposed to the avdd 1 and avss levels used by the gpio pins. the pin has an active pull - up in this case. 16 iovdd digital i/o supply voltage . iovdd voltage ranges from 2 v to 5 v. iovdd is independent of avdd2. f or example , iovdd can be operated at 3 v when avdd2 equals 5 v , or vice versa. if avss is set to ? 2.5 v , the voltage on iovdd must not exceed 3.6 v . 17 dgnd digital ground. 18 regcap d digital ldo regulator output . this pin is f or decoupling purposes only. decouple this pin to dgnd using a 1 f cap acitor . 19 gpio 0 general - purpose input/output . the pin is referenced between avdd1 and avss levels . 20 gpio 1 general - purpose input/output . the pin is referenced between avdd1 and avss levels. 21 ain0 analog input 0. selectable through the crosspoint multiplexer . 22 ain1 analog input 1. selectable through the crosspoint multiplexer . 23 ain2 analog input 2. selectable through the crosspoint multiplexer . 24 ain3 analog input 3. selectable through the crosspoint multiplexer .
data sheet ad7176- 2 rev. 0 | page 11 of 68 typical performance characteristics figure 5. noise (avdd1 = 5 v, avdd2 = 5 v, iovdd = 3.3 v, v ref = 5 v, output data rate = 5 sps) figure 6. noise (avdd1 = 5 v, avdd2 = 5 v, iovdd = 3.3 v, v ref = 5 v, output data rate = 10 ksps) figure 7. noise (avdd1 = 5 v, avdd2 = 5 v, iovdd = 3.3 v, v ref = 5 v, output data rate = 250 ksps) figure 8. noise distribution histogram (avdd1 = 5 v, avdd2 = 5 v, iovdd = 3.3 v, v ref = 5 v, output data rate = 5 sps) figure 9. noise distribution histogram (avdd1 = 5 v, avdd2 = 5 v, v ref = 5 v, iovdd = 3.3 v, output data rate = 10 ksps) figure 10 . noise distribution histogram (avdd1 = 5 v, avdd2 = 5 v, v ref = 5 v, iovdd = 3.3 v, output data rate = 250 ksps) 8388358 8388357 8388356 8388355 8388354 8388353 0 100 200 300 400 500 adc code sample 1 1037-005 8388375 8388330 0 2000 4000 6000 8000 adc code sample 8388335 8388340 8388345 8388350 8388355 8388360 8388365 8388370 1 1037-006 8388420 8388260 0 15,000 10,000 5000 adc code sample 8388280 8388300 8388320 8388340 8388360 8388380 8388400 1 1037-007 450 0 8388354 occurence adc code 50 100 150 200 250 300 350 400 8388356 8388356 1 1037-008 800 0 8388336 occurence adc code 8388372 100 200 300 400 500 600 700 8388342 8388348 8388354 8388360 8388366 1 1037-009 500 0 8388282 occurence adc code 8388408 8388302 8388324 8388344 8388366 8388386 50 100 150 200 250 300 350 400 450 1 1037-010
ad7176- 2 data sheet rev. 0 | page 12 of 68 figure 11 . noise vs. common - mode input voltage (avdd1 = 5 v, avdd2 = 5 v, iovdd = 3.3 v, v ref = 2.5 v) figure 12 . noise vs. master clock (avdd1 = 5 v, avdd2 = 5 v, iovdd = 3.3 v, v ref = 2.5 v) figure 13 . 50 hz input tone, ?0.5 dbfs input fft (avdd1 = 5 v, avdd2 = 5 v, iovdd = 3.3 v, v ref = 2.5 v , output data ra te = 1 ksps ) figure 14 . 1 khz input tone, ?0.5 dbfs input fft (avdd1 = 5 v, avdd2 = 5 v, iovdd = 3.3 v, v ref = 2.5 v , output data rate = 50 ksps ) figure 15 . 50 hz input tone, ?6 dbfs input fft (avdd1 = 5 v, avdd2 = 5 v, iovdd = 3.3 v, v ref = 2.5 v , output data rate = 1 ksps ) figure 16 . 1 khz input tone, ?6 dbfs input fft (avdd1 = 5 v, avdd2 = 5 v, iovdd = 3.3 v, v ref = 2.5 v , output data rate = 50 ksps ) 12 10 8 6 4 2 0 0 1 5 4 3 2 rms noise (v) v cm (v) 250ksps 10ksps 1ksps 1 1037-012 11.0 10.5 8.0 8.5 9.0 9.5 10.0 0 5 10 15 rms noise (v) master clock frequency (mhz) 1 1037-016 0 ?180 0 500 amplitude (db) frequency (hz) ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 50 100 150 200 250 300 350 400 450 1 1037-017 0 ?160 0 25k 5k 10k 15k 20k amplitude (db) frequency (hz) ?140 ?120 ?100 ?80 ?60 ?40 ?20 1 1037-019 0 ?180 0 500 amplitude (db) frequency (hz) ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 50 100 150 200 250 300 350 400 450 1 1037-020 0 ?160 0 25k 5k 10k 15k 20k amplitude (db) frequency (hz) ?140 ?120 ?100 ?80 ?60 ?40 ?20 1 1037-022
data sheet ad7176- 2 rev. 0 | page 13 of 68 figure 17 . 1 khz input tone , ? 0.5 dbfs input fft (avdd1 = 5 v, avdd2 = 5 v, iovdd = 3.3 v, v ref = 2.5 v , output data rate = 250 ksps ) figure 18 . 1 khz input tone, ?6 dbfs input fft (avdd1 = 5 v, avdd2 = 5 v, iovdd = 3.3 v, v ref = 2.5 v , output data rate = 250 ksps ) figure 19 . internal reference settling time (extended) (avdd1 = 5 v, avdd2 = 5 v, iovdd = 3.3 v) figure 20 . common - mode rejection ratio (10 hz to 70 hz) (avdd1 = 5 v, avdd2 = 5 v, iovdd = 3.3 v, 20 sps enhanced filter) figure 21 . internal reference settling time (avdd1 = 5 v, avdd2 = 5 v, iovdd = 3.3 v) figure 22 . common - mode rejection ratio vs. frequency (avdd1 = 5 v, avdd2 = 5 v, iovdd = 3.3 v, output data rate = 250 ksps) 0 ?160 0 100k 120k 20k 40k 60k 80k amplitude (db) frequency (hz) ?140 ?120 ?100 ?80 ?60 ?40 ?20 1 1037-023 0 ?160 0 100k 120k 20k 40k 60k 80k amplitude (db) frequency (hz) ?140 ?120 ?100 ?80 ?60 ?40 ?20 1 1037-026 0.10 0.05 0 ?0.05 ?0.10 0 10 20 30 40 50 error (%) time (seconds) 1 1037-030 0 ?160 10 70 cmrr (db) frequency (hz) ?140 ?120 ?100 ?80 ?60 ?40 ?20 20 30 40 50 60 1 1037-031 1.0 0.5 0 ?0.5 ?1.0 0.00001 0.1 0.01 0.001 0.0001 error (%) time (seconds) from standby ? reference off from power-down 1 1037-032 0 ?20 ?40 ?60 ?80 ?100 ?120 1 10 100 1k 10k 100k 1m cmrr (db) frequency (hz) 1 1037-033
ad7176- 2 data sheet rev. 0 | page 14 of 68 figure 23 . power supply rejection ratio vs. frequency (avdd1 = 5 v, avdd2 = 5 v, iovd d = 3.3 v) 0 ?160 1 10m 1m 100k 10k 1k 100 10 power supply rejection (db) frequency (hz) ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 1 1037-034
data sheet ad7176- 2 rev. 0 | page 15 of 68 noise performance an d resolution table 6 show s the rms noise and the noise free (peak - to - peak) resolution of the ad7176 - 2 for various output data rates and filters. the numbers given ar e for the bipolar input range with an external 5 v ref erence. these numbers are typical and are generated with a differential input voltage of 0 v when the adc is continuously converting on a single channel. it is important to note that the peak - to - peak r esolution is calculated based on the peak - to - peak noise. the peak - to - peak resolution represents the resolution for which there is no code flicker. table 6 . rms noise and peak -to - peak resolution vs . output data rate 1 sinc5 + sinc1 filter (default) sinc3 filter output data rate (sps) noise (v rms) peak - to - peak resolution (bits) noise (v rms) peak - to - peak resolution (bits) 250,000 9.7 17.2 220 12.8 62,500 5.4 18.2 5.1 18.3 10,000 2.5 19 1 .8 19.8 1000 0.82 20.8 0.62 21 60 0.46 21.4 0.32 22 50 0.42 21.7 0.31 22 16. 7 0.42 21.7 0.29 22.4 5 0.32 22.2 0.29 22.4 1 selected rates only, 1000 samples.
ad7176- 2 data sheet rev. 0 | page 16 of 68 getting started the ad7176 - 2 offers the user a fast settling, high resolution, multiplexed adc with high levels of configurability. ? two fully differential or four single - ended analog inputs. ? crosspoint multiplexer selects any analog input combina - tion as the input signals to be converted, routing them to the modulator positive or negative input. ? fully differential input, single - ended relative to any analog input and pseudo differential configuration available. ? per channel configurability up to four different setups can be defined. a separate setup can be mapped to each of the channels. each setup allows the user to configure: ? gain and offset correction ? filter type ? o utput data rate ? reference source selection (internal/external) the ad7176 - 2 includes a precision 2.5 v low drift (2 ppm/c) band gap internal reference. this reference can be selected to be used for the adc c onversions, reducing the external com - ponent count. alternatively, the reference can be output to the refout pin to be used as a low noise biasing voltage for the external circuitry. an example of this is using the refout signal to set the input common mod e for an external driving amplifier. the ad7176 - 2 includes two separate linear regulator blocks for both the analog and digital circuitry. the analog ldo regulates the avdd2 supply to 2 v supplying the adc cor e. the user can tie the avdd1 and avdd2 supplies together for easiest connection. if there is already a clean analog supply rail in the system in the range of 2 v to 5 v, the user can also choose to connect this to the avdd2 input, allowing for lower power dissipation. figure 24 . typical connection diagram dgnd ain4 AD7176-2 iovdd cs sync/error sync/error regcapd refout avss 0.1f regcapa avdd2 avdd1 xtal1 gpio 1 4 2 3 1 24 23 22 21 19 20 9 10 11 12 13 14 15 16 17 18 7 8 5 6 6 8 5 3 1 4 7 2 ref? ref+ 2.5v reference output 4.7f 0.1f 0.1f vout gnd nc v in 0.1f 4.7f vin 0.1f adr445brz iovdd avdd2 0.1f avdd1 0.1f cx1 16mhz cx2 0.1f 1f 0.1f 1f general purpose io 0 and 1 output high = avdd output low = avss for single supply case output high = 5v output low = gnd optional external crystal circuitry capacitors gpio 0 clkin optional external clock input ain0 ain1 ain2 ain3 ain4 see analog input section for further details in0 in4 in1 in2 in3 gpio 0 gpio 1 clki0/xtal2 dout/rdy din sclk cs dout/rdy din sclk 1 1037-051
data sheet ad7176- 2 rev. 0 | page 17 of 68 the linear regulator for the digital iovdd supply performs a similar function, regulating the input voltage applied at the iovdd pin to 2 v for the internal digital filtering. the serial interface signals always operate from the iovdd supply seen at the pin. this means that if 3.3 v is applied to the iovdd pin, the interface logic inputs and outputs operate at this level. the ad7176 - 2 can be used across a wide variety of applications, providing high resolutio n and accuracy. a sample of these scenarios is as follows: ? fast scanning of analog input channels using the internal multiplexer . ? fast scanning of analog input channels using an external multiplexer . ? h igh resolution at lower speeds in either channel scanni ng or adc per channel applications. ? single adc per channel: the fast low latency output allows further application specific filtering in an external micro - controller, dsp, or fpga. power supplies the ad7176 - 2 has three independent power supply pins: avdd1, avdd2, and iovdd. avdd1 powers the front - end circuitry, including the crosspoint multiplexer. avdd1 is referenced to avss and avdd1 ? avss = 5 v only. this can be a single 5 v supply or a 2.5 v split supply. the split supply operation allows for true bipolar inputs. when using split supplies, the absolute maximum ratings (see the absolute maximum ratings section) must be kept in mind. avdd2 powers the internal 1.8 v analog ldo regulator. this regulator powers the adc core. avdd2 is referenced to avss, and av dd2 C avss can range from 5 v to 2 v. iovdd powers the internal 1.8 v digital ldo regulator. this regulator powers the digital logic of the adc . iovdd sets the voltage levels for the spi interface of the adc. iovdd is refer - enced to dgnd, and iovdd ? dgnd can vary from 5 v to 2 v. digital communicatio n the ad7176 - 2 has a 3 - or 4 - wire spi interface that is compatible with qspi?, microwire ? , and dsps. the interface operates in spi mode 3 and can be operated with cs tied low. in spi mode 3, the sclk idles high, the falling edge of sclk is the drive edge, and the rising edge of sclk is the sample edge. this means that data is clocked out on the falling/drive edge and data is clocked in on the rising/sample edge. figure 25 . spi mode 3 sclk edges accessing the adc register map the communications register controls access to the full register map of the adc. this register is an 8 - bit write only register. on power - up or after a reset, the digital interface defaults to a state where it is expected a write to the communications register; therefore, all communication begins by writing to the communications register. the data written to the communications register determines which register is being accessed and if the next operation is a read or write. the register address bits (r a [5:0]) de termine the specific register to which the read or write operation applies. when the read or write operation to the selected register is complete, the interface returns to its defaults state, where it expects a write operation to the communications registe r. in situations where interface synchronization is lost, a write operation of at least 64 serial clock cycles with din high returns the adc to its default state by resetting the entire part, including the register contents. alternatively, if cs is being used with the digital interface, returning cs high sets the digital interface to its default state and aborts any current operation. figure 26 and figure 27 illustrate writing to and reading from a register by first writing the 8 - bit command to the communications register followed by the data for that register. figure 26 . writing to a register (8- bit command with register address followed by data of 8, 16, or 24 bits; data length is dependent on the register selected) figure 27 . reading from a register (8- bit command with register address foll owed by data of 8, 16, or 24 bits; data length on dout is dependent on the register selected) drive edge sample edge 1 1037-052 din sclk cs 8-bit command 8 bits, 16 bits, or 24 bits of data cmd dat a 1 1037-053 din sclk cs 8-bit command 8 bits, 16 bits, 24 bits, or 32 bits of data cmd d at a dout/rd y 1 1037-054
ad7176- 2 data sheet rev. 0 | page 18 of 68 reading the id register is the recommended method for verifying correct communication with the part. the id registers is a read only register and contains the value 0x0c9x for the ad7176 - 2 . the communication register and id register details are described in table 7 and table 8 . table 7 . com munications register reg name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x00 comms [7:0] wen r/ w ra 0x00 w table 8 . id register reg name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x07 id [15:8] id[15:8] 0x0c9x r [7:0] id[7:0]
data sheet ad7176- 2 rev. 0 | page 19 of 68 configuration overvi ew figure 28 provides an overview of the configuration flow, divided into the following three blocks: ? adc and interface mode configuration (labeled a in figure 28) ? adc setups (labeled b in figure 28) ? channel map configuration (labeled c in figure 28) figure 28 . configuration flow write t o adc mode register and inter f ace mode register; set u p high leve l adc peripherals and inter f ace set u p configur a tion; four possible adc setups using dedic a ted fi l ter, offse t , and gain registers select the positive and neg a tive input for each adc channe l and ma p each channe l t o a setu p a b c 1 1037-055
ad7176- 2 data sheet rev. 0 | page 20 of 68 adc and interface mode configur ation the adc mode register and the interface mode register (see block a in figure 28) configure the core peripherals to be used by the ad7176 - 2 and the mode for the digital interface. adc mode register the adc mode register is used primarily to set the conversion mode of the adc to either continuous or single conversion. the user can also selec t the standby and power - down modes as well as any of the calibration modes. in addition, this register contains the clock source select bits and the internal reference enable bits. the reference select bits are contained in the setup configuration register s (see the adc setup s section for more information) . interface mode register the interface mode register is used to configure the digital interface operation. this re gister allows the user to control data - word length, crc enable, data + status read and continuous read mode. both register details are shown in table 9 and table 10. for more information , see the digital interface section. table 9 . adc mode register reg name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x01 adcmode [15:8] ref_en reserved sing_cyc reserved delay 0x8000 rw [7:0] reserved mode clocksel reserved table 10 . interface mode register reg name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x02 ifmode [15:8] reserved alt_sync iostrength reserved dout_reset 0x0000 rw [7:0] contread data_stat reg_check reserved crc_en reserved wl16
data sheet ad7176- 2 rev. 0 | page 21 of 68 adc setup s the ad7176 - 2 has four independent setup s (see block b in figure 28) . each setup consists of the following four registers: ? s etup configuration register ? f ilter configuration register ? o ffse t register ? gain register for example, setup 0 consists of setup configuration 0 , filter configuration 0 , offset 0 , and g ain 0 . the setup is selectable from the channel map registers detailed in the channel map configuration section. th is allows each channel to be assigned to a separate setup; therefore, each channel is fully configurable because each setup has its own filter, offset, and gain register. table 11 thr ough table 14 show the four registers that are associated with setup 0. setup configuration register the setup configuration registers allow the user to select the output coding of the adc by selecting bet ween bipolar and unipolar. in bipolar mode , the adc accept s negative differential input voltages , and the output coding is offset binary. in unipolar mode , the adc accepts only positive differential voltages , and the coding is straight binary. in either ca se , the input voltage must be within the supply voltages. the user can also select the reference source using this register. there are three options avail able an internal 2.5 v reference, an external reference connected between ref+ and ref ? pins , or avdd1 C avs s . filter configuration register the filter configuration register is used to select which digital filter is used at the output of the adc modulator. the order of the filter and the output data rate is selected by setting the bits in this re gister. for more information , see the digital filters section. offset register the offset register holds the offset calibration coefficient for the adc. the power - on reset value of the offset register is 0x800000. the offset register is a 24 - bit read/write register. the power - on reset value is automatically overwritten if an internal or system zero - scale calibration is initiated by the user or if the offset register is written to by the user. gain register the gain register is a 24 - bit register that holds the gain calibration coefficient for the adc. the gain registers are read/write registers. these registers are configured at power - on with factory c alibrated coefficients. therefore, every device has different default coefficients. the default value is automatically overwritten if a system full - scale calibration is initiated by the user or if the gain register is written to by the user . for more infor mation on calibration , see the operating modes section. table 11 . setup configuration 0 register reg name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x20 setupcon0 [15:8] reserved bi_unipolar0 reserved 0x1020 rw [7:0] reserved ref_sel0 reserved table 12 . filter configuration 0 register reg name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x28 f i ltco n0 [15:8] sinc3_map0 reserved enhfilten0 enhfilt0 0x0000 rw [7:0] reserved order0 odr0 table 13 . offset 0 register reg name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x30 offset0 [23:16] offset0[23:16] 0x800000 rw [15:8] offset0[15:8] [7:0] offset0[7:0] table 14 . gain 0 register reg name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x38 gain0 [23:16] gain0[23:16] 0x5xxxx0 rw [15:8] gain0[15:8] [7:0] gain0[7:0]
ad7176- 2 data sheet rev. 0 | page 22 of 68 channel map configuration the ad7176 - 2 has four independent channels (see block c in figure 28) . the user can select which of the four setups is use d for each channel . this allows for per channel configuration. channel map register th e channel map register is used to select which of the five analog input pins are used as either the positive analog input or the negative analog input for that channel. this register also contains a channel enable/disable bit and the setup selection bits , which are used to pick which of the four available setups are used for this channel. when the ad7176 - 2 is operating in continuous conversion mode with more than one channel enabled , the channel sequencer cycle s through the enabled chan nels in sequential order, from chann el map 0 to channel map 3 . if a c hannel is disabled, it is skipped by the sequencer. deta ils of the channel map register for channel 0 are shown in table 15. table 15 . channel map register reg name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x10 chmap0 [15:8] ch_en0 reserved setup_sel0 reserved ainpos0[4:3] 0x8001 rw [7:0] ainpos0[2:0] ainneg0
data sheet ad7176- 2 rev. 0 | page 23 of 68 circuit description analog input the ad7176 - 2 has five analog input pins : ain0, ain1, ain2, ain3 , and ain4. each of these pins connects to the internal crosspoint multip lexer. the crosspoint multiplexer enables any of these inputs to be configured as an input pair, either pseudo differential or fully differential. the ad7176 - 2 can have up to four active channels. when more th an one channel is enabled , the channels are automatically sequenced in order. the output of the multiplexer is connected directly to the switched - capacitor input of the adc. the simplified analog input circuit is shown in figure 29. figure 29 . simplified analog input circuit the cs1 and cs2 capacitors have a magnitude in the or der of a number of pico f arads each. this capacitance is the comb in ation of both the sampling capacitance and the parasitic capacitance. the average input current to the ad7176 - 2 changes linearly with the differential input voltage at a rate of 48 a/ v. each of the analog inputs must be buffered externally not on ly to provide the varying input current with differential input amplit ude but also to settle the switched - capacitor input to allow for accurate sampling. recommended amplifiers for this purpose are discussed in the driver amplifiers section. fully differential inputs because the ain0 to ain4 analog inputs are connected to a crosspoint multiplexer , any combi nation of signals can be used to create an analog input pair. this allows the user to select two fully differential inputs or four pseudo differential inputs. if two fully differential input paths are connected to the ad7176 - 2 , using ain0 / ain1 as one differential input pair and ain2 / ain3 as the second differential input pair is recommended. this is due to the relative locations of these pins to each other . all analog inputs s hould be decoupled to avss . pseudo differential inputs the user can also choose to measure four differ ent single - ended analog inputs. in this case , each of the analog inputs is converted as being th e difference between the single - ended input to be measured and a set analog input common pin. because there is a crosspoint multiplexer , the user can set any of the a nalog inputs as the common pin. an example of such a scenario is to connect the ain4 pin to avss or to the refout voltage ( that is, avss + 2.5 v ) and select this input when configuring the crosspoint multiplexer. when using the ad7176 - 2 with pseudo differential inputs , the inl specification is degraded. driver amplifiers to d r iv e the analog input switch capacitor , an external amplifier is required. details of three r ecommended amplifiers for the ad7176 - 2 are shown in the driver amplifiers section . each of the amplifiers can run from a single 5 v voltage rail. ain0 ain1 a vdd1 a vss a vss a vss a vdd1 a vss ain2 a vdd1 ain4 a vdd1 ain3 a vdd1 a vss ?1 cs1 cs2 +in ?in ?2 ?2 ?1 1 1037-056
ad7176- 2 data sheet rev. 0 | page 24 of 68 ad8475 the ad8475 features an a ttenuating input stage of 0.8 or 0.4 (using integrated precision resistors) , allowing inputs in the 10 v range with a single 5 v supply and a 3 ma current consumption to be used . the ad8475 perform s single - ended to differential conversion s , allows easy setting of th e common - mode output , and drives the ad7176 - 2 with a differential input. figure 30 shows a typical connection to the ad7176 - 2 , where two ad8475 amplifiers attenuate two differential inputs and then drive th e ad7176 - 2 inputs. the common - mode output of the ad8475 is set by connecting the internal , buffered 2.5 v reference of the ad7176 - 2 to the vocm pin of the ad8475 . the output of the ad8475 to the ad 7176 - 2 is fully differential with a fixed common mode of 2.5 v. the output of the ad8475 amplifier is connected to an rc network. the rc network , as shown in figure 30, includes r in = 10 ? ; c1, c2 = 270 pf ; and c3 = 680 pf. the rc circuit acts to provide the dynamic charge required by the ad7176 - 2 switched sampling capacitors while isolating the amplifier output from any kickback from the dynamic switched capacitor input. the configuration of the ad8475 in figure 30 shows a fully differential s ignal source with a gain of 0.4 . the ad8475 can a lso be set up to convert single - ended signals to fully differential inputs. gro un d the ? in 0.4 input and apply the single - ended input to the +in 0.4 inpu t. figure 30 . ad8475 driving two differential inputs of the ad7176 - 2 ad8475 AD7176-2 12.5v low impedance voltage source in0 r in c1 0.1 f c2 c3 r in ?in 0.4x +5v +in 0.4x vocm in1 ad8475 12.5v low impedance voltage source in2 r in c1 c2 c3 r in +in 0.4x ?in 0.4x vocm in3 adr445 microcontroller host 0.1 f 5v vref 0.1 f 4.7 f +5v 5.5v to 18v 0.1 f 0.1 f 2.5v 0.1 f 2 6 3 ref? avss 7 avdd1 8 avdd2* *avdd2 can be supplied by voltages ranging from 2v to 5.5v. ref+ 24 23 22 21 ain0 ain1 ain2 4 refout ain3 0.1 f 0.1 f +5v cs 11 12 13 14 dout/rdy din sclk 1 1037-057
data sheet ad7176- 2 rev. 0 | page 25 of 68 ad8656 the ad8656 is a l ow noise , dual precision cmos amplifier . the ad8656 allows the user to connect a signal of interest directly to a high impedance, low noise, low offset amplifier input that can drive the ad7176 - 2 switch ed capaci tor input. the ad8656 can operate from a single 5 v supply. when using an external 5 v reference such as the adr445 in conjunction with the ad7176 - 2 , the ad8656 output can swing to within ? 1 dbfs ( which equates to a differential input of 4.45 v) of the ad c input range . a simple configuration for use of the ad8656 is to connect the amplifiers in a configuration for a gain of more than 1 . each of the ad7176 - 2 analog inputs has its own amplifier. this allows the user to co nnect either full y differential inputs or single - ended inputs to the ad7176 - 2 . the example shown in figure 31 is configured with two fully differential inputs connecting to the ain0/ain1 pair and the ain2/ain3 pair . the high impedance input to the amplifier allows the user to band - limit the input with a suitable passive filter rc combination. the gain of the con figuration used is set by the r g and r f resistors . to improve accuracy , use precision resistors for r g and r f . setting r g = r f = 1 k ? results in a gain of 2 for the circuit. the matching of the rg and rf resistors directly affects the gain error of the cir cuit. the drift and matching of these resistors affect the gain error drift of the circuit. a 10 ? source resistor (r s ) is placed b etween the feedback resistor ( r f ) and the amplifier output . this resistor acts to isolate the amplifier from any kickback from the adc input and does not directly affect the gain error of the circuit. the output of each of the amplifier pairs is connected directly to a network of decoupling and differential capac itors prior to being connect ed to the ad7176 - 2 analog inputs. the capacitor network shown in figure 31 includes c1, c2 = 270 pf and c3 = 680 p f. t h e capacitor network acts to provide the dynamic charge required by the ad7176 - 2 switched sampling ca pacitors . t he circuit example in figure 31 requires inclusion of two precision gain resistors per amplifier (r g and r f ) . choose t he value, precision, and matching of such resistors according to the requirement s of the application. figure 31 . dual ad8656 amplifiers driving the ad7176 - 2 AD7176-2 c1 c2 c3 adr445 2 microcontroller host ad8656 0.1 f r f r g r s r s +5v +5v r f r g in0 0 to +2.5v input range 0 to +2.5v input range in1 5v vref 0.1 f 4.7 f 5.5v to 18v 0.1 f 0.1 f 2 6 3 ref? avss 7 avdd1 8 avdd2 1 1 avdd2 can be supplied by voltages ranging from 2v to 5.5v. 2 using adr444 (4.096v reference) in place of the adr445 as shown in this example would allow the entire cct to be operated from a single 5v supply rail. ref+ 22 21 c1 c2 c3 ad8656 r f r g r s r s 0.1 f r f r g in2 0 to +2.5v input range 0 to +2.5v input range in3 ain0 ain1 0.1 f 0.1 f +5v cs 11 12 13 14 dout/rdy din sclk 24 23 ain2 ain3 1 1037-158
ad7176- 2 data sheet rev. 0 | page 26 of 68 ada4940 the ada4940 - 1 / ada4940 - 2 is an alternate option to driv e the ad7176 - 2 . it is a low noise, low distorti on fully differential amplifier with very low power consumption (1.25 ma of quiescent current). the ad7176 - 2 refout pin can be us ed to connect to the ada4940 - 1 / ada4940 - 2 to set the common - mode output to 2.5 v. this option requires the use of external resistors to set the gain of the amplifier. ad7176 - 2 reference the ad7176 - 2 offers the user the option of either supplying an external reference to the r ef+ and r ef ? pin s of the device or allow ing the use of the internal 2.5 v , low noise, low drift reference. select the reference source to be used by the analog input by setting the ref_sel x bits (bits [5:4] ) in the s etup c onfiguration r egisters appropriately. the structure of the setup configuration 0 register is shown in table 16. the ad7176 - 2 defaults on power - up to use the internal 2.5 v reference . external reference the ad7176 - 2 has a fully differential reference input applied through the ref+ and ref ? pins. standard low noise , low drift voltage references , such as the adr445 , adr444 , and adr441 , are recommended for use. the external reference should be applied to the ad7176 - 2 reference pins as shown in figure 32. the output of any external reference should be decoupled to avss. as shown in figure 32, the adr44 5 output i s decoupled with a 0.1 f cap acitor at its output for stability purposes. the output is then connected to a 4.7 f ca pacitor , which act s as a reservoir for any dynamic charge required by the adc , and foll owed by a 0.1 f decoupling capacitor at the ref+ input. this capacitor is placed as close as possible to the ref+ and ref ? pins. the ref ? pin is connected directly to the avss potential. on power - up of the ad7176 - 2 , the internal reference is enabled by default and is output on the refout pin. when an external reference is used instead of the internal reference to supply the ad7176 - 2 , attention must be paid to th e output of the refout pin. if the internal reference is not being used elsewhere in the application , ensure that the refout p in is not hardwired to avss because t his will dr aw a large current on power - up. on power - up if the internal reference is not being used , write to the adc m ode register, disabling the internal reference. this is controlled by the ref_en bit ( bit 15) in the adc m ode register and is shown in table 17. figure 32 . external reference adr445 connected to ad7176 - 2 reference pins table 16 . setup configuration 0 r egister reg name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x20 setupcon0 [15:8] reserved bi_unipolar0 reserved 0x1020 rw [7:0] reserved ref_sel0 reserved table 17. adc mode register reg name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x01 adcmode [15:8] ref_en reserved sing_cyc reserved delay 0x8000 rw [7:0] reserved mode clocksel reserved 2 3 ref? ref+ 4.7f 0.1f 1 1 1 1 1 0.1f 0.1f 5.5v to 18v adr445 2 5v vref AD7176-2 1 all decoupling is to avss. 2 any of the adr44x family references may be used. adr444 or adr441 both enable reuse of the 5v analog supply needed for avdd1 to power the reference vin. 1 1037-159
data sheet ad7176- 2 rev. 0 | page 27 of 68 internal reference the ad7176 - 2 includes its own low noise, low drift voltage reference. the internal reference has a 2.5 v output. the internal reference is output on the refout pin after th e ref_en bit in the adc mode re gister is set and is decoupled to avss with a 0.1 f capacitor. the ad7176 - 2 internal reference is enabled by default on power - up a nd is selected as the reference source for the adc. the refout signal is buffered prior to being output to the pin. the signal can be used extern ally in the circuit as a common - mode source for external amplifier configurations. this is shown in figure 30 in the driver amplifiers section , where the refout pin supplies the vocm input of the ad8475 amplifier. ad7176 - 2 clock source the ad7176 - 2 requires a master clock of 16 mhz. the ad7176 - 2 can source its sampling clock from one of three scenarios: ? internal oscillator ? external crystal ? external clock source all output data rates listed in the data sheet relate to a master clock rate of 16 mhz. using a lower clock frequency from , for instance , an external source will scale any listed data rate proportionally. to achieve the specified data rates, particularly rates for rejection of 50 hz and 60 hz, a 16 mhz clock should be used. the source of the master clock is selected by setting the cl oc ksel bits (bits[3:2]) in the a dc mode register as shown in table 17. the default operation on power - up and reset of the ad7176 - 2 is to operat e with the internal oscillator. internal oscillator the internal oscillator runs at 16 mhz and can be used as the adc master clock. it is the default clock source for the ad7176 - 2 and is specified with an accuracy of 2 .5 %. there is an option to allow the internal clock oscillator to be output on the ad7176 - 2 clkio/xtal2 pin. the clock output is driven to the iovdd logic level. use of this option can affect the dc performance of the ad7176 - 2 due to the disturbance introduced by the output d river. the extent to which the performance is affected depends on the iovdd voltage supply. higher iovdd voltages create a wider logic output swing from the driver and affect performance to a greater extent. this i s further exaggerated if the io strength bi t is set at higher iovdd levels (see table 25 for more information ). external crystal if higher precision , lower jitter clock sources are required , the ad7176 - 2 has the ability to use an ext ernal crystal to generate the master clock. the crystal is connected to the xtal1 and xtal2 pins. a recommended crystal for use is the fa - 20h a 16 mh z , 10 ppm , 9 p f crystal from epson - toyocom which is available in a surface - mounted package. as shown in figure 33, allow for two capacitors to be inserted from the traces connecting the crystal to the xtal1 and xtal2 pins. these capacitors allow for circuit tuning. connect these capacitors to the dgnd pin . the value for these capacitors depend s on the length and capacitance of the trace connections between the crystal and the xtal1 and xtal 2 pins. th erefore , the values of these capacitors differ depending on the pcb layout and the crystal employed . as a result, empirical testing of the circuit is required. figure 33 . external crystal connections external clock the ad7176 - 2 can also use an externally supplied clock. in systems where this is desirable , the external clock is routed to the clkio pin. in this configuration , the clkio pin accepts the externally sourced clock an d routes it to the modulator. the logic level of this clock input is defined by the voltage applied to the iovdd pin. 1 1037-160 9 10 cx1 cx2 xtal1 clkio/xtal2 *decouple t o dgnd. AD7176-2 * *
ad7176- 2 data sheet rev. 0 | page 28 of 68 digital filters the ad7176 - 2 has three flexible filter options to allow for optimization of noise, settling time , and rejection : ? sinc5 + sinc1 filter ? sinc3 filter ? enhanced 50 hz and 60 hz rejection filters figure 34 . digital filter block diagram the filter and output data rate is configured by setting the appropriate bits in the filter configuration register for the selected setup. see the register details section for more information. sinc5 + sinc1 filter the sinc5 + sinc1 filter is targeted at fast switching multiplexed applications and achieves single cycle settling at output data rates of 10 k sps and lower. the sinc5 block output is fixed at the maximum rate of 250 k sps , and the sinc1 block output data rate can be varied to control the final adc output data rate. figure 35 shows the f requency domain response of the sinc5 + sinc1 filter at a 50 sps output data rate. the sinc5 + sinc1 filter has a slow roll - off over frequency and narrow notches. figure 35 . sinc5 + sinc1 filter response at 50 sps odr the output data rates with the accompanying settling time and rms noise for the sinc5 + sinc1 filter are shown in table 18. table 18. ad7176 - 2 output data rate (odr) , noise, settling time (t settle ) , and rejection using the sinc5 + sinc1 f ilter output data rate (sps) 1 settling time 1 switching rate (hz) 1 notch frequency (hz) rej ection 1 hz (db) 2 noise (v rms) peak - to - peak resolution with 5 v reference (bits) 250,000 20 s 50,000 250,000 9.7 17.25 125,000 24 s 41,667 125,000 7.4 17.6 62,500 32 s 31,250 62,500 5.4 18.1 50,000 36 s 27,778 50,000 5 18.2 31,250 48 s 20,833 31,250 4 18.5 25,000 56 s 17,857 25,000 3.6 18.7 15,625 80 s 12,500 15,625 2.7 19.1 10,000 100 s 10,000 11,905 2.5 19.2 5 000 200 s 5 000 5 435 1.8 19.7 2 500 400 s 2 500 2 604 1.3 20.2 1 000 1.0 ms 1 000 1 016 0.82 20.8 500 2.0 ms 500.0 504 0.63 21.2 400 2.516 ms 400 400.00 0.62 21.2 200 5.0 ms 200.0 200.64 0.47 21.6 100 10.0 ms 100.0 100.16 0.46 21.7 60 16.68 ms 460 60.00 34 db (60 hz) 0.43 21.7 50 20.016 ms 50 50.00 34 db (50 hz) 0.42 21.8 20 50.0 ms 20.00 20.01 0.42 21.8 16.667 60.02 ms 16.66 16.67 0.42 21.8 10 100.02 ms 10.00 10.00 34 db (50 hz and 60 hz) 0.38 22 5 200.02 ms 5.00 5.00 0.32 22.1 1 the sett ling time has been rounded to the nearest microsecond. this is reflected in the output data rate and switching rate. switchin g rate = 1 tsettle. 2 master clock = 160 mhz. sinc1 sinc5 sinc3 50hz and 60hz post filter 1 1037-058 0 ?120 0 150 100 50 filter gain (db) frequency (hz) 11037-059 ?100 ?80 ?60 ?40 ?20
data sheet ad7176- 2 rev. 0 | page 29 of 68 sinc3 filter the sinc3 filter achieves the best single - channel noise performance at lower rates and is , therefore , most suitable for single - channel applications. the sinc3 filter always ha s a settling time equal to t settle = 3/ output data rate figure 36 shows the frequency domain filter response for the sinc3 filter. the sinc3 filter has good roll - off over frequency and has wide notches for good notch frequency rejection. figure 36 . sinc3 filter response the output data rates with the accompanying settling time and rms noise for the sinc3 filter are shown in table 19. it is possible to finely tune the output data rate for the sinc3 filter by setting the sinc3_map bit in the filter configuration register. if this bit is set, the mapping of the filter register changes to directly program the decimation rate of the sinc3 filter. all other options are eliminated. the data rate when on a single channel can be calculated using the following equation : 4:0] filtconx[1 f rate data output mod = 32 where: f mod is the modulator rate and is 8 mhz . filtcon x [14:0] are the contents on the filter configuration register excluding the msb. for example, an output data rate of 50 sps can be achieved with sinc3_map enabled by setting the filtcon x [14:0] bits to a value of 5000. single cycle settlin g the ad7176 - 2 can be configure d by setting the sing_cyc bit in the adc mode register so that only fully settled data is output , thus effectively putting the adc into a single cycle settling mode. this mode achieve s single cycle settling by reducing the output d ata rate to be equal to the settling time of the adc for the selected output data rate. this bit has no effect with the sinc5 + sinc1 at output data rates of 10 k sps and lower. figure 37 shows a step on the analog input with this mode disabled and the sinc3 filter selected. it takes at least three cycles after the step change for the output to reach the final settled value. figure 37 . step input without single cycle settling figure 38 shows the same step on the analog input but with single cycle settling enabled. it takes at least a single cycle for the output to be fully settled. t he output data rate is now reduced to equal the settling time of the filter at the selected output data rate. figure 38 . step input with single cycle settling 0 ?120 0 150 100 50 filter gain (db) frequency (hz) 11037-060 ?100 ?80 ?60 ?40 ?20 ?110 ?90 ?70 ?50 ?30 ?10 1/odr analog input fully settled adc output 1 1037-061 t settle analog input fully settled adc output 1 1037-062
ad7176- 2 data sheet rev. 0 | page 30 of 68 table 19. ad7176 - 2 output data rate (odr) , noise, settling time (t settle ) , and rejection using the sinc3 filter o utput data rate (sps) 1 settling time (ms) 1 switching rate 1 (hz) notch frequency (hz) rejection 1 hz (db) 2 noise (v rms) peak - to - peak resolution with 5 v reference (bits) 250,000 0.012 83,333 250,000 220 12.8 125,000 0.024 41,667 125,000 27 15.9 62,500 0.048 20,833 62,500 5.1 18.3 50,000 0.060 16,667 50,000 4.3 18.5 31,250 0.096 10,417 31,250 3.2 18.8 25,000 0.120 8333 25,000 2.7 19 15,625 0.192 5208 15,625 2.3 19.4 10,000 0.300 3333 10,000 1.8 19.8 5000 0.600 1667 5000 1.3 20.2 2500 1.200 833 2500 0.91 20.5 1000 3.000 333.3 1000 0.62 21 500 6.000 166.7 500 0.49 21.4 400 7.500 133.3 400 0.45 21.7 200 15.000 66.7 200 0.37 22 100 30.000 33.3 100 0.33 22 59.94 50.004 20.00 59.94 100 (60 hz) 0.32 22 49.96 60.000 16.67 49.96 100 (50 hz) 0.31 22 20 150.000 6.67 20 0.31 22 16.667 180.000 5.56 16.667 0.29 22.4 10 300.000 3.33 10 100 (50 hz and 60 hz) 0.29 22.4 5 600.000 1.67 5 0.29 22.4 1 the settling time has been rounded to the nearest microsecond. this is reflected in the output data rate and switching rate. switching rate = 1 t settle . 2 master clock = 160 mhz.
data sheet ad7176- 2 rev. 0 | page 31 of 68 enhanced 50 hz and 60 hz rejection filters the e nhanced filter s are design ed to provide rejection of 50 hz and 60 hz simultaneously and to allow the user to trade off settling time and rejection. these filters can operate up to 27.27 sps or can reject up to 90 db of 50 hz 1 hz and 60 hz 1 hz interference . these filters are realized by post filter ing the output of the sinc5 + sinc1 filter. for this reason, the sinc5 + sinc1 filter must be selected when using the enhanced filters. table 20 shows the output data rates with the accompanying settling time, rejection, and rms noise. figure 39 to figure 46 show the frequency domain plots of the responses from the enhanced filters. table 20. ad7176 - 2 enhanced filters output data rate, noise , settling time (t settle ) , and rejection using the enhanced filters output data rate (sps) settling time (ms) simultaneous rejection of 50 hz 1 hz and 60 hz 1 hz (db) 1 noise (v rms) peak - to - peak resolution (bits) comments 27.27 36.67 47 0.15 23.26 see figure 39 and figure 40 25 40.0 62 0.14 23.36 see figure 41 and figure 42 20 50.0 85 0.125 23.53 see figure 43 and figure 44 16.667 60.0 90 0.125 23.53 see figure 45 and figure 46 1 master clock = 160 mhz.
ad7176- 2 data sheet rev. 0 | page 32 of 68 figure 39 . dc to 600 hz, 27.27 sps odr, 36.67 ms settling time figure 40 . zoom in 40 hz to 70 hz, 27.27 sps o dr, 36.67 ms settling time figure 41 . dc to 600 hz, 25 sps odr, 40 ms settling time figure 42 . zoom in 40 hz to 70 hz, 25 sps odr, 40 ms settling time figure 43 . dc to 600 hz, 20 sps odr, 50 ms settling time figure 44 . zoom in 40 hz to 70 hz, 20 sps odr, 50 ms settling time 0 ?100 0 600 filter gain (db) frequency (hz) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 100 200 300 400 500 1 1037-063 0 ?100 40 70 filter gain (db) frequency (hz) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 45 50 55 60 65 1 1037-064 0 ?100 40 filter gain (db) frequency (hz) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 600 100 200 300 400 500 1 1037-065 0 ?100 40 70 filter gain (db) frequency (hz) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 45 50 55 60 65 1 1037-066 0 ?100 0 600 filter gain (db) frequency (hz) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 100 200 300 400 500 1 1037-067 0 ?100 40 70 filter gain (db) frequency (hz) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 45 50 55 60 65 1 1037-068
data sheet ad7176- 2 rev. 0 | page 33 o f 68 figure 45 . dc to 600 hz,16. 66 7 sps odr, 60 ms settling time figure 46 . zoom in 40 hz to 70 hz, 16. 66 7 sps odr, 60 ms settling time 0 ?100 0 600 filter gain (db) frequency (hz) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 100 200 300 400 500 1 1037-069 0 ?100 40 70 filter gain (db) frequency (hz) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 45 50 55 60 65 1 1037-070
ad7176- 2 data sheet rev. 0 | page 34 of 68 operating modes continuous conversio n mode continuous conversion is the default power - up mode. the ad7176 - 2 converts continuously, and the rdy bit in the status register goes low each time a conversion is complete. if cs is low, the dout/ rdy line also goes low when a conversion is complete. to read a conversio n, the user writes to the commu nications register, indicating that the next operation is a read of the data register. when the data - word has been read from the data register, dout/ rdy goes high. the user can read this register additional times, if required. however, the user must ensure that the data register is not being accessed at the completion of the next con - version ; otherwise the new conversion word will be lost. when several channels are enabled, the adc automatically sequences through the enabled channels, performing one conversion on each channel. when all channels have been converted, the sequence starts again with the first channel. the channels are con verted in order from lowest enabled channel to highest enabled channel. the data register is updated as soon as each conversion is available. the dout/ rdy pin pulses low each time a conversion is available. the user can then read the c onversion while the adc converts the next enabled channel . if the data_stat bit in the interface mode register is set to 1, the contents of the status register , along with the conversion data, are output each time the data register is read. the status re gister indicates the channel to which the conversion corresponds. figure 47 . continuous conversion mode din sclk dout/rdy cs 0x44 0x44 data data 1 1037-071
data sheet ad7176- 2 rev. 0 | page 35 o f 68 continuous read mode in continuous read mode, it is not required to write to the communications register before reading adc data; just apply the required number of sclks after dout/ rdy goes low to indicate the end of a conversion. when the conversion is read, dout/ rdy returns high until the next conversion is available. in this mode, the data can be read only once. the user must also ensure that the data - word is read before the next conversion is complete. if the user has not read the conversion before the completion of the next conversion or if insufficient serial clocks are applied to the ad7176 - 2 to read the word, the serial output register is reset when the next conversion is complete, and the new conversion is placed in the output serial register. the adc must be configured for continuous conversion mode to use continuous read mode. to enable continuous read mode , set the cont read bit in the interface mode register. when this bit is set, the only serial interface operations possible are reads from the data register. to exit con - tinuous read mode , issue a dummy read of the adc data register command (0x44) while rdy is low. alternatively , apply a software reset , that is, 64 sclks with cs = 0 and din = 1 . this reset s the adc and all register contents. these are the only commands that the interface recognizes after it is placed in continuous read mode. din should be held low in continuous read mode until an instruction is t o be written to the device. if multiple adc channels are enabled, each channel is output in turn, with the status bits being appended to the data if data_stat is set in the interface mode register. the status register indicates the channel to which the conversion corresponds. figure 48 . continuous read mode din sclk dout/rd y cs 0x02 data data data 0x0800 1 1037-072
ad7176- 2 data sheet rev. 0 | page 36 of 68 single conversion mode in single conversion mode, the ad7176 - 2 performs a single conversion and is placed in standby mode after the conversion is complete. dout/ rdy goes low to indicate the completion of a conversion . when the data - word has been read from the data register, dout/ rdy goes high. the data register can be read several times, if required, even when dout/ rdy has gone high. if several channels are enabled, the adc automatically sequences through the enabled channels and perfo rms a conversion on each channel. when a conversion is started, dout/ rdy goes high and remains high until a valid conversion is available and cs is low. as soon as the conversion is available, dout/ rdy goes low. the adc then selects the next channel and begins a conversion. the user can read the present conversion while the next conversion is being performed. as soon as the next conversion is complete, the data register is updated; therefore, t he user has a limited period in which to read the conversion. when the adc has performed a single conversion on each of the selected channels, it returns to standby mode. if the data_stat bit in the interface mode register is set to 1, the contents of the status register , along with the conversion, are output each time the data register is read . the two lsbs of the status register indicate the channel to which the conversion corresponds . figure 49 . single conversion mode din sclk dout/rdy cs 0x01 0x44 data 0x8010 1 1037-073
data sheet ad7176- 2 rev. 0 | page 37 of 68 standby and power - down modes in standby mode, most blocks are powered down. the ldos remain active so that registers maintain their contents. the internal reference remains active if enabled , and the c rystal oscillator remains active if selected. to power down the reference in standby mode, set the ref_en bit in the adc mode regsiter to 0 . to power down the clock in standby mode , set the clocksel bits in the adc mode register to 00 ( internal oscillator ) . in power - down mode, all blocks are powered down, including the ldos. all registers lose their contents , and the gpio outputs are placed in tristate. to prevent accidental entry to power - down mode, the adc must first be placed into standby mode. exiting power - down mode requires 64 sclks with cs = 0 and din = 1, that is, a serial interface reset. a delay of 500 s is recommended before issuing a subsequent serial interface command to allow the ldo to power up. calibration modes the ad7176 - 2 provides three calibration modes that can be used to eliminate the offset and gain errors on a per setup basis : ? internal zero - scale calibration mode ? system zero - scale calibration mode ? system full - scale calibration mode only one channel can be active during calibration. after each conversion, the adc conversion result is scaled using the adc calibration registers before being written to the data register. the default value of the offset regist er is 0x800000 , and the nominal value of the gain register is 0x555555. the calibration range of the adc gain is from 0.4 v ref to 1.05 v ref . the following equations show the calculations that are used . in unipolar mode, the ideal relationship that is, not taking into account the adc gain error and offset error is as follows: 2 0x400000 ) 0x800000 ( 2 75 . 0 23 ? ? ? ? ? ? ? ? = gain offset v v data ref in in bipolar mode, the ideal relationship that is, not taking into account the adc gain error and offset error is as follows: 0x800000 0x400000 0x800000) ( 2 0.75 23 + ? ? ? ? ? ? ? ? = gain offset v v data ref in to start a calibration, write the relevant value to the mode bits in the adc mode register . the dout/ rdy pin and the rdy bit in the status register go high when the calibration initiates. when the calibration is complete, the content s of the corresponding offset or gain register are updated, the rdy bit in the status register is reset, the dout/ rdy pin returns low (if cs is low), and the ad7176 - 2 reverts to standby mode . during an internal offset calibration, the selected positive analog input pin is disconnected , and both modulator inputs are connected internally to the selected negative analog input pin. for this reason , it is necessary to ensure that the voltage on the selected negative analog input pin does not exceed the allowed limits and is free from excessive noise and interference. system calibrations, however, expect the system zero - scale (offset) and system full - scale (gain) voltages to be applied to the adc pins before initiating the calibration modes. as a result , errors external to the adc are removed. from an operational point of view, treat a calibration like another adc conversion. an offset calibration, if required, must always be performed before a full - scale calibration. set the system software to monitor the rdy bit in the status register or the dout/ rdy pin to determine the end of a calibration via a polling sequence or an interru pt - driven routine. all calibrations require a time equal to the settling time of the selected filter and output data rate to be completed. an internal offset calibration, system zero - scale calibration, and system full - scale calibration can be performed at any output data rate. using lower output data rates results in better calibration accuracy and is accurate for all output data rates. a new calibration is required for a given channel if the reference source for that channel is changed. the offset error is typically 4 0 v and an offset calibration reduces the offset error to the order of the noise. the gain error is factory calibrated at ambient temperature. following this calibration, the gain error is typically 0.001%. the ad7176 - 2 provides the user with access to the on - chip calibration registers, allowing the microprocessor to read the calibration coefficients of the device and to write its own calibration coefficients. a read or write of the offset and ga in registers can be performed at any time except during an internal or self - calibration.
ad7176- 2 data sheet rev. 0 | page 38 of 68 digital interface t he programmable functions of the ad7176 - 2 are via the spi serial interface. the serial interface of the ad7176 - 2 consists of four signals: cs , din, sclk, and dout/ rdy . the din line is used to transfer data into the on - chip registers , and dout/ rdy is used to access data from the on - chip registers. sclk is the serial clock input for the device, and all data transfers (either on din or on dout/ rdy ) occur with respect to the sclk signal. the dout/ rdy pin also function s as a data - ready signal, with the line going low if cs is low when a new data - word is available in the data register. the pin is reset high when a read operation from the data register is complete. the dout/ rdy pin also goes high before updating the data register to indicate when not to read from the device to ensure that a data read is not attempted while the register is being updated. cs is used to select a device. it can be used to decode the ad7176 - 2 in systems where several components are connected to the serial bus. figure 2 and figure 3 show timing diagrams for interfacing to the ad7176 - 2 using cs to decode the part. figure 2 shows the timing for a read operation from the ad7176 - 2 , and figure 3 shows the timing for a write operation to the ad7176 - 2 . it is possible to read from the data register several times even though the dout/ rdy line returns high after the f irst read operation. however, care must be taken to ensure that the read operations are completed before the next output update occurs. in continuous read mode, the data register ca n be read only once. the serial interface can operate in 3 - wire mode by tyi ng cs low. in this case, the sclk, din, and dout/ rdy lines are used to communicate with the ad7176 - 2 . the end of the conversion can also be monitored using the rdy bit in the status register . the serial interface can be reset by writing 64 sclks with cs = 0 and din = 1. a r eset returns the interface to the state in which it expects a write to the communications regist er. this operation resets the contents of all registers to their power - on values. following a reset, allow a period of 500 s before addressing the serial interface. c hecksum protection the ad7176 - 2 has a checksum mode , which can be used to improve interface robustness. using the checksum ensures that only valid data is written to a register and allows data read from a register to be validated. if an error occurs during a register write, the crc_error bit is set in the status register. however, to ensure that the register write was successful , the register should be read back and checksum verified. for crc checksum calculations during a write operation, the following polynomial is always used : x 8 + x 2 + x + 1 during read operations, the user can select between this polynomial and a similar xor function. the xor function requires less time to process on the host microcontroller than the polynomial - based checksum . the crc _ en bits in the interface mode register enable and disable the checksum and allow the user to select between the polynomial check and the simple xor check. the checksum is appended to the end of each read and write transaction. the checksum calculation for th e write transaction is calculated using the 8 - bit command word and the 8 - to 24 - bit data. for a read transaction , the checksum is calculated using the command word and the 8 - to 32 - bit data output. figure 50 and figure 51 show spi write and read transaction s, respectively. figure 50 . spi write transaction with crc figure 51 . spi read transaction with crc if checksum protection is enabled when continuous read mode is active , there is an implied read data command of 0x44 before every data transmission that needs to be accounted for when calculating the checksum value. this ensures a non zero checksum value even if the adc data equals 0x000000. 8-bit command 8-bit crc u p t o 24-bit input cs data crc cs din sclk 1 1037-074 8-bit command 8-bit crc u p t o 32-bit input cmd data crc cs din sclk dout/ rd y 1 1037-075
data sheet ad7176- 2 rev. 0 | page 39 of 68 crc calculation polynomial the checksum , which is 8 - bits wide , is generated using the polynomial x 8 + x 2 + x + 1 to generate the checksum , the data is left shifted by eight bits to cre ate a number ending in eight logic 0s. the polynomial is aligned so that its msb is adjacent to the leftmost logic 1 of the data . an xor (exclusive or) function is applied to the data to produce a new , shorter number. the polynomial is again aligned so that its msb is adjacent to the left most logic 1 of the new result , and the procedure is repeated. this process is repeated until the original data is reduced to a value less than the polynomial. this is the 8 - bit checksum. example of a polynomial crc calculation 24- bit word: 0x654321 ( eight command bits and 16 - bit data) an example of generating the 8 - bit checksum using the polynomial based checksum is as follows: initial value 011001010100001100100001 01100101010000110010000100000000 left shifte d eight bits x 8 + x 2 + x + 1 = 100000111 polynomial 100100100000110010000100000000 xor result 100000111 polynomial 100011000110010000100000000 xor result 100000111 polynomial 11111110010000100000000 xor result 100000111 polynomial value 1111101110000100000000 xor result 100000111 polynomial value 111100000000100000000 xor result 100000111 polynomial value 11100111000100000000 xor result 100000111 polynomial value 1100100100100000000 xor result 100000111 polynomial value 100101010100000000 xor result 100000111 polynomial value 101101100000000 xor result 100000111 polynomial value 1101011000000 xor result 100000111 polynomial value 101010110000 xor result 100000111 polynomial value 1010001000 xor result 100000111 polynomial value 10000110 checksum = 0x86.
ad7176- 2 data sheet rev. 0 | page 40 of 68 xor calculation the checksum, which is 8 - bits wide, is generated by splitting the data into bytes and then performing an xor of the bytes. example of an xor calculation 24- bit word: 0x654321 ( eight command bits and 16 - bit data) using the previous example, divide into three bytes : 0x65, 0x43, and 0x21 01100101 0x65 01000011 0x43 00100110 xor result 00100001 0x21 00000111 crc
data sheet ad7176- 2 rev. 0 | page 41 of 68 general - purpose i/o the ad7176 - 2 has two general - purpose digital input/output pins: gpio0 and gpio1. these are enabled using the ip_en0/ ip_en 1 or op_en0/ op_en 1 bits in the gp iocon register. when the gpio0 or gpio1 pin is enabled as an input , the logic level at the pin is contained in the data0 or data 1 bit , respectively . when the gpio0 or gpio1 pin is enabled as an output , the gp_ data0 or gp_ data 1 bits , respectively, determine the logic level output at the pin. the logic levels for these pins a re referenced to av dd 1 a nd avss ; therefore , o utputs have an amplitude of 5 v. if an external multiplexer is used to increase the channel count, the multiplexer logic pins can be controlled via the ad7176 - 2 gpio pins. with the mux_io bit , the gpios timi ng is controlled by the adc; therefore , the channel change is synchroni z ed with the adc , eliminating any need for external synchroni z ation. the sync / error pi n can also be used as a general - purpose output. when err_en bit s in the gp iocon register are set to 1 1, the sync / error pin operates as a general - purpose output. in this configuration, the err _ dat bit in the gp iocon register determines the logic level output at the pin. the logic level for the pin is referenced to iovdd and dgnd , and the sync / error pin has an active pull - up. 16- bit /24 - bit conversions by default, the ad7176 - 2 generates 24 - bit conversions. however, the width of the conversions can be reduced to 16 bit s . setting bit wl16 in the interface mode register to 1 rounds all data conversions to 16 bits. clearing this bit sets the width of the data conversions to 24 bit s. serial interface reset (dout_reset) the serial interface is reset when each read operation is complete. the instant at which the serial interface is reset is programmable. by default, the serial interface is reset after a period of time following the last sclk rising edge , the sclk edge on which the lsb is read by the processor. by setting bit dout_reset in the interface mode register to 1, the instant at which the interface is reset is controlled by the cs rising edge. in this case, the dout/ rdy pin continues to output the lsb of the register being read until cs is taken high. only on the cs rising edge is the interface reset. this configuration is useful if the cs signal is used t o frame all read operations. if cs is not used to frame all read operation s, dout_reset should be set to 0 so that the interface is reset following the last sclk edge in the read operation. synchronization ( sync / error ) normal synchroni z ation when the sync_en bit i n the gp iocon register is set to 0, the sync / error pin functions as a synchronization pin. the sync input allows the user to reset the modulator and the digital filter without affecting any of the setup conditions on the part. this allows the user to start gathering samples of the analog input from a known point in time, that is, the rising edge of sync . this pin must be low for at least one master clock cycle to ensure that synchronization occurs. if multiple ad7176 - 2 devices are operated from a common master clock, they can be synchronized so that their data registers are updated simultaneously. this is normally done after each ad7176 - 2 has performed its own calibration or has calibration coefficients loaded into its calibration reg isters. a falling edge on the sync pin resets the digital filter and the analog modulator and places the ad7176 - 2 into a consistent known state. while the sync pin is low, t he ad7176 - 2 is maintained in this state. on the sync rising edge, the modulator and filter are taken out of this reset state , and on the next master clock edge, the part starts to gather input samples again. the part is taken out of reset on the master clock falling edge following the sync low - to - high transition. therefore, when multiple devices are being synchronized, the sync pin should be t aken high on the master clock rising edge to ensure that all devices begin sampling on the master clock falling edge. if the sync pin is not taken high in sufficient time, it is possible to have a difference of one master clock cycle between the devices; that is, the instant at which conversions are available differs from part to part by a maximum of one master clock cycle. the sync pin can also be used as a start conversion command. in this mode, the rising edge of sync starts a conversion, and the falling edge of rdy indicates when the conversion is complete. the settling time of the filter has to be allowed for each data register update. alternate synchroni z ation setting bit alt_sync in the interface mode register to 1 enables an alternate synchronization scheme . t he sync_en bit in the gp iocon register must be set to 1 to enable this alternate scheme. in this mode, the sync pin operates as a start conversion com - mand when several channels of the ad7176 - 2 are enabled. when sync is taken low, the adc completes the conversion on the current channel, selects the next channel in the sequence , and then waits until sync is taken high to commence the conversion. the rdy pin goes low when the conversi on is complete on the current channel , and the data register is updated with the corresponding conversion. therefore, the sync command does not interfere with the sampling on the currently selected channel but allows the user to control the instant at which the conversion begins on the next channel in the sequence. the mode can be used only when several channels are enabled. it is not recommended to use this mode when a single channel is enabled.
ad7176- 2 data sheet rev. 0 | page 42 of 68 error flags the status register contains three error bits adc_error, crc_error, and reg_error that flag errors with the adc conversion , errors with the crc check, and errors due to changes in the registers, respectively . in addition, th e error pin can indicate that an error has occurred . adc_ error the adc_ error bit in the status register flags any errors that occur during the conversion process. the flag is set when an over - voltage or undervoltage occurs on the analog inputs. the adc also outputs all 0s or all 1s when an undervoltage or overvoltage occurs. this flag is reset only when the overvoltage/undervoltage is removed. it is not reset by a read of the data register. crc_error if the crc value that accompanies a write operation does not correspond w ith the information sent, the crc_error flag is set. the flag is reset as soon as the statu s register is explicitly read. reg_error this flag is used i n conjunction with the reg_ch ec k bit in the interface mode register. when the reg_ch ec k bit is set, the ad7176 - 2 monitors the values in the on - chip registers. if a bit changes, the reg_error bit is set. therefore, for writes to the on - chip regis ters, reg_ch ec k should be set to 0. when the registers have been updated, t he ref_chk bit can be set to 1 . the ad7176 - 2 calculates a check sum o f the on - chip registers. if one of the register values has changed , the reg_error bit is set. if an error is flagged, the reg_ch ec k bit must be set to 0 to clear the reg_error bit in the status register. the register check function does not monitor the data register, status register , or interface mode register. error pin when the sync_en bit in the gp iocon register i s set to 1 and bit alt_sync in the int erface mode register is set to 0, the sync / error pin functions as a n error input/output pin or a general - purpose output pin. the err_en bits in the gp iocon register determine the function of the pin. wit h err_en bits are set to 1 0, the pin f unctions as an open - drain error output pin. the three error bits in the status register ( adc_ error, crc_error , and reg_error) are or ed, inverted , and mapped to the error pin. therefore, the error pin indicates that an error has occurred. the status register must be read to identify the error s ource. wh en err_en bits are set to 0 1 , the error pin functions as an erro r input pin. the error pin of another component can be connected to the ad7176 - 2 error pin so that the ad7176 - 2 indicates when an error occurs on either itself or the external component. the value on the error pin is inverted and or ed with the errors from the adc conversion , and the result is indicated via the adc_ error bit in the status register. the value o f the error pin is reflected in the err _ dat bit in the status register. the error pin is disabled when the err_en bits are set to 0 0 . when the err_en1 bits are set to 1 1, the error pin operates as a general - purpose output. data_stat the contents of the status register can be appended to each con - version on the ad7176 - 2 . this is a useful function if several channels are enabled. each time a conversion is output, the conte nts of the status register are appended. the two lsbs of the status register indicate to which channel the conversion corresponds. in addition, the user can determine if any errors are being flagged by the error bits . io strength the serial interface can operate with a power supply as low as 2 v. however, a t this low voltage, the dout/ rdy pin may not have sufficient drive strength if there is moderate parasitic capacitance on the board or the sclk frequency is high. the io strength bit in the interface mode register increases the drive strength of the dout/ rdy pin.
data sheet ad7176- 2 rev. 0 | page 43 of 68 grounding and layout the analog inputs and reference inputs are differential and , therefore, most of the vo ltages in the analog modulator are common - mode voltages. the high common - mode rejection of the part removes common - mode noise on these inputs. the analog and digital supplies to the ad7176 - 2 are independent and separately pinned out to minimize coupling between the analog and digital sections of the device. the digital filter provides rejection of broadband noise on the power supplies, except at integer multiples of the master clock frequency . the digital filter also removes noise from the analog and reference inputs , provided that these noise sources do not saturate the analog modulator. as a result, the ad7176 - 2 is more immune to noise interfer ence than a conventional high resolution converter. however, because the resolution of the ad7176 - 2 is high and the noise levels from the converter are so low, care must be taken with regard to grounding and l ayout. the printed circuit board (pcb) that houses the adc must be designed so that the analog and digital sections are separated and confined to certain areas of the board. a minimum etch technique is generally best for ground planes because it results in the best shielding. in any layout, the user must keep in mind the flow of currents in the system, ensuring that the paths for all return currents are as close as possible to the p aths the currents took to reach their destinations . avoid running digital li nes under the device because this couples noise onto the die and allow s the analog ground plane to run under the ad7176 - 2 to prevent noise coupling. the power supply lines to the ad7176 - 2 must use as wide a trace as possible to provide low impedance paths and reduce glitches on the power supply line. shield fast switching signals like clocks with digital ground to prevent radiating noise to other sections of the board and never run clock signals near the analog inputs. avoid crossover of digital and analog signals. run traces on opposite sides of the board at right angles to each other. this reduces the effects of feed through on the board. a microstrip technique is by far the best but is not always possible with a double - sided board. in this technique, the component side of the bo ard is dedicated to ground planes, whereas signals are placed on the solder side. good decoupling is important when using high resolution adcs. the ad7176 - 2 has three power supply pins av dd1, av dd2, and iovdd. the avdd1 and avdd2 pins are referenced to avss, and the iovdd pin is referenced to dgnd. avdd1 and avdd2 should be decoupled with a 10 f tantalum capacitor in parallel with a 0.1 f capacitor to avss on each pin. the 0.1 f capacitor should be placed as close as possible to the device on each supply, ideally right up against the device. iovdd should be decoupled with a 10 f tantalum capacitor in parallel w ith a 0.1 f capacitor to dgnd. all analog inputs should be decoupled to avss. if an external refer ence is us ed, the ref+ and ref ? pins should be decoupled to avss. the ad7176 - 2 also has two on - board ldo regulators one that regulates the avdd2 supply and one that regulates the iovdd supply. for t he regc a pa pin , it is recommended that 1 f and 0.1 f capacitor s to avs s be used. similarly, for the regcapd pin , it is recommended that 1 f and 0.1 f capacitor s to dgnd be used . if using the ad7176 - 2 for split supply operation , a separate plane must be used for avss.
ad7176- 2 data sheet rev. 0 | page 44 of 68 register summary table 21. ad7176 - 2 register summary reg name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x00 comms [7:0] wen r/ w ra 0x00 w 0x00 status [7:0] rdy adc_error crc_error reg_error reserved channel 0x80 r 0x01 adcmode [15:8] ref_en reserved sing_cyc reserved delay 0x8000 rw [7:0] reserved mode clocksel reserved 0x02 ifmode [15:8] reserved alt_sync iostrength reserved dout_reset 0x0000 rw [7:0] contread data_stat reg_check reserved crc_en reserved wl16 0x03 regcheck [23:16] register_check[23:16] 0x000000 r [15:8] register_check[15:8] [7:0] register_check[7:0] 0x04 data [23:16] data[23:16] 0x000000 r [15:8] data[15:8] [7:0] data[7:0] 0x06 gpiocon [15:8] reserved mux_io sync_en err_en err_dat 0x0800 rw [7:0] reserved ip_en1 ip_en0 op_en1 op_en0 gp_data1 gp_data0 0x07 id [15:8] id[15:8] 0x0c9x r [7:0] id[7:0] 0x10 chmap0 [15:8] ch_en0 reserved setup_sel0 reserved ainpos0[4:3] 0x8001 rw [7:0] ainpos0[2:0] ainneg0 0x11 chmap1 [15:8] ch_en1 reserved setup_sel1 reserved ainpos1[4:3] 0x0001 rw [7:0] ainpos1[2:0] ainneg1 0x12 chmap2 [15:8] ch_en2 reserved setup_sel2 reserved ainpos2[4:3] 0x0001 rw [7:0] ainpos2[2:0] ainneg2 0x13 chmap3 [15:8] ch_en3 reserved setup_sel3 reserved ainpos3[4:3] 0x0001 rw [7:0] ainpos3[2:0] ainneg3 0x20 setupcon0 [15:8] reserved bi_unipolar0 reserved 0x1020 rw [7:0] reserved ref_sel0 reserved 0x21 setupcon1 [15:8] reserved bi_unipolar1 reserved 0x1020 rw [7:0] reserved ref_sel1 reserved 0x22 setupcon2 [15:8] reserved bi_unipolar2 reserved 0x1020 rw [7:0] reserved ref_sel2 reserved 0x23 setupcon3 [15:8] reserved bi_unipolar3 reserved 0x1020 rw [7:0] reserved ref_sel3 reserved 0x28 filtcon0 [15:8] sinc3_map0 reserved enhfilten0 enhfilt0 0x0000 rw [7:0] reserved order0 odr0 0x29 filtcon1 [15:8] sinc3_map1 reserved enhfilten1 enhfilt1 0x0000 rw [7:0] reserved order1 odr1 0x2a filtcon2 [15:8] sinc3_map2 reserved enhfilten2 enhfilt2 0x0000 rw [7:0] reserved order2 odr2 0x2b filtcon3 [15:8] sinc3_map3 reserved enhfilten3 enhfilt3 0x0000 rw [7:0] reserved order3 odr3 0x30 offset0 [23:16] offset0[23:16] 0x800000 rw [15:8] offset0[15:8] [7:0] offset0[7:0] 0x31 offset1 [23:16] offset1[23:16] 0x800000 rw [15:8] offset1[15:8] [7:0] offset1[7:0] 0x32 offset2 [23:16] offset2[23:16] 0x800000 rw [15:8] offset2[15:8] [7:0] offset2[7:0] 0x33 offset3 [23:16] offset3[23:16] 0x800000 rw [15:8] offset3[15:8] [7:0] offset3[7:0]
data sheet ad7176- 2 rev. 0 | page 45 of 68 reg name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x38 gain0 [23:16] gain0[23:16] 0x5xxxx0 rw [15:8] gain0[15:8] [7:0] gain0[7:0] 0x39 gain1 [23:16] gain1[23:16] 0x5xxxx0 rw [15:8] gain1[15:8] [7:0] gain1[7:0] 0x3a gain2 [23:16] gain2[23:16] 0x5xxxx0 rw [15:8] gain2[15:8] [7:0] gain2[7:0] 0x3b gain3 [23:16] gain3[23:16] 0x5xxxx0 rw [15:8] gain3[15:8] [7:0] gain3[7:0]
ad7176- 2 data sheet rev. 0 | page 46 of 68 register details communications regis ter address: 0x00, reset: 0x00, name: comms table 22. bit descriptions for comms bits bit name settings description reset access 7 wen this bit must be low to begin communications with the adc. 0x0 w 6 r/ w this bit determines if the command is a read or write operation. 0x0 w 0 write command 1 read command [5:0] ra the register address bits determine which register is to be read from or written to as part of the current communication. 0x00 w 000000 status register 000001 adc mode register 000010 interface mode register 000011 register checksum register 000100 data register 000110 gpio configuration register 000111 id register 010000 channel map 1 register 010001 channel map 2 register 010010 channel map 3 register 010011 channel map 4 register 100000 setup configuration 1 register 100001 setup configuration 2 register 100010 setup configuration 3 register 100011 setup configuration 4 register 101000 filter configuration 1 register 101001 filter configuration 2 register 101010 filter configuration 3 register 101011 filter configuration 4 register 110000 offset 1 register 110001 offset 2 register 110010 offset 3 register 110011 offset 4 register 111000 gain 1 register 111001 gain 2 register 111010 gain 3 register
data sheet ad7176- 2 rev. 0 | page 47 of 68 status register address: 0x00, reset: 0x80, name: status the status register is an 8 - bit register that contains adc and serial interface status information. it can optionally be appended to the data register by setting the data_stat bit in the interface mode register. table 23 . bit descript ions for status bits bit name settings description reset access 7 rdy the status of rdy is output to the dout/ rdy pin whenever cs is low and a register is not being read. this bit goes low when the adc has written a new result to the data register. in adc calibration modes, this bit goes low when the adc has written the calibration result. rdy is brought high a utomatically by a read of the data register. 0x1 r 0 new data result available 1 awaiting new data result 6 adc_error this bit by default indicates if an adc overrange or underrange has occurred. the adc result will be clamped to full scale if this happens. this bit is updated when the adc result is written and is cleared by removing the overrange or underrange condition on the analog inputs. 0x0 r 0 no error 1 error 5 crc_error this bit indicates if a crc error has taken place during a register write. for register reads, the host microcontroller determines if a crc error has occurred. this bit is cleared by a read of this register. 0x0 r 0 no error 1 crc error 4 reg_error this bit indicates if the content of one of the internal registers has changed from the value calculated when the register integrity check was activated. the check is activated by setting the reg_check bit in the interface mode register. this bit is cleare d by clearing the reg_check bit. 0x0 r 0 no error 1 error [3:2] reserved these bit s are reserved. 0x0 r [1:0] channel these bits indicate which channel was active for the adc conversion whose result is currently in the data register. this may be different from the channel currently being converted. the mapping is a direct map from the channel m ap r egister; therefore, chan nel 0 results in 0x0 and channel 3 results in 0x3. 0x0 r 00 channel 0 01 channel 1 10 channel 2 11 channel 3
ad7176- 2 data sheet rev. 0 | page 48 of 68 adc mode register address: 0x01, reset: 0x8000, name: adcmode the adc mode register controls the operating mode of the adc and the master clock selection. a write to the adc mode register resets the filter and the rdy bits and starts a new conversion or calibration. table 24 . bit descriptions for adcmode bits bit name settings description reset access 15 ref_en enables internal reference and outputs a buffered 2.5 v to the refout pin. 0x1 rw 0 disabled 1 enabled 14 reserved this bit is reserved and should be set to 0. 0x0 r 13 sing_cyc this bit can be used when only a single channel is active to set the adc to only output at the settled filter data rate. 0x0 rw 0 disabled 1 enabled [12:11] reserved these bit s are reserved and should be set to 0. 0x0 r [10:8] delay these bits allow a programmable delay to be added after a channel switch to allow for settling of external circuitry before the adc starts processing its input . 0x0 rw 000 0 001 4 s 010 16 s 011 40 s 100 100 s 101 200 s 110 500 s 111 1 ms 7 reserved this bit is reserved and should be set to 0. 0x0 r [6:4] mode these bits control the operating mode of the adc. details can be found in the operating modes section. 0x0 rw 000 continuous conversion mode 001 single conversion mode 010 standby mode 011 power - down mode 100 internal offset calibration 110 system offset calibration 111 system gain calibration [3:2] clocksel this bit is used to select the adc clock source. selecting internal oscillator also enables the internal oscillator. 0x0 rw 00 internal oscillator 01 internal oscillator output on x tal2 pin 10 external clock input on xtal2 pin 11 external crystal on xtal1 and xtal2 pins [1:0] reserved these bi t s are reserved and should be set to 0. 0x0 r
data sheet ad7176- 2 rev. 0 | page 49 of 68 interface mode regis ter address: 0x02, reset: 0x0000, name: ifmode the interface mode register configures various serial interface options. table 25 . bit descriptions for ifmode bits bit name settings description reset access [15:13] reserved these bit s are reserved and should be set to 0. 0x0 r 12 a lt_ sync this bit enables a different behavior of the error \ sync pin to allow the use of error \ sync as a control for conversions when cycling channels (see the des cription of the sync _en bit in the gpio configuration register for details). 0x0 rw 0 disabled 1 enabled 11 iostreng t h this bit controls the drive strength of the dout pin. this bit should be set when reading from the serial interface at high speed with low iovdd supply and moderate capacitance. 0x0 rw 0 disabled (default) 1 enabled [10:9] reserved these bit s are reserved and should be set to 0. 0x0 r 8 dout_reset this bit prevents the dout/ rdy pin from switching from outputting dout to outputting rdy soon after the last rising edge of sclk during a read operation. instead, the dout/ rdy pin will continue to output the lsb of the data until cs goes high. this allows for longer hold times for the spi master to sample the lsb of the data. when this bit is set, cs must not be tied low. 0x0 rw 0 disabled 1 enabled 7 contread this enables continuous read of the adc data register. the adc should be configured in continuous conversion mode to use continuous read. for more details, see the operating modes section. 0x0 rw 0 disabled 1 enabled 6 data_stat this enables the status register to be appended to the data register when read so that channel and status information are transmitted with the data. this is the only way to be sure that the channel bits read from the status register correspond to the data in the data register. 0x0 rw 0 disabled 1 enabled 5 reg_check this bit enables a register integrity checker, which can be used to monitor any change in the value of the user registers. to use this feature, all other registers should be configured as desired, with this bit cleared. then write to this register to set the reg_check bit to 1. if the contents of any of the registers change, the reg_error bit is set in the status register. to clear the error, the reg_check bit should be set to 0. neither the interface mode register nor the adc data or status register is included in the registers that are checked. if a register needs to have a new value written, this bit should first be cleared; otherwise, an error will be flagged falsely when t he new register contents are written. 0x0 rw 0 disabled 1 enabled 4 reserved this bit is reserved and should be set to 0. 0x0 r
ad7176- 2 data sheet rev. 0 | page 50 of 68 bits bit name settings description reset access [ 3 :2] crc_en enables crc protection of register reads/writes. crc increases the number of bytes in a serial interface transfer by one. see the crc calculation section for more details. 0x0 0 rw 0 0 disabled . 01 xor checksum e nabled for register read transactions. register writes will still use crc with th ese bit s set. 1 0 crc c hecksum e nabled for read and write transactions. 1 reserved this bit is reserved and should be set to 0. 0x0 r 0 wl16 changes the adc data register to 16 bits. the adc is not reset by a write to the interface mode register; therefore, the adc result will not be rounded to the correct word length immediately after writing to these bits. the first new adc result will be cor rect. 0x0 rw 0 24- bit data 1 16- bit data register check address: 0x03, reset: 0x000000, name: regcheck this register check register is a 24 - bit checksum calculated by exclusively or'ing the contents of the user registers. the reg_check bit in the interface mode register must be set for this to operate; otherwise, the register reads 0. table 26 . bit descriptions for regcheck bits bit name settings description reset access [23:0] register_check this register contains the 24 - bit checksum of user registers when the reg_check bit is set in the interface mode register. 0x000000 r data register address: 0x04, reset: 0x000000, name: data the data register contains the adc conversion result. the encoding is offset binary, or it can be changed to unipolar by the bi_unipolar bit in the setup configuration register. reading the data register brings the rdy bit and pin high if they had been low. the adc result can be read multiple times; however, because rdy has been brought high, it is not possible to know if another adc result is imminent. the adc will not write a new result into the data register if the register is currently being read. table 27 . bit descriptions for data bits bit name settings description reset access [23:0] data this register contains the adc conversion result. if data_stat is set in the interface mode register, then the status register is appended to this register when read, making this a 32 - bit register. if wl16 is set in the i nterface m ode r egister , then this register is rounded to 16 bits . 0x000000 r
data sheet ad7176- 2 rev. 0 | page 51 of 68 gpio configuration register address: 0x06, reset: 0x0800, name: gpiocon the gpio configuration register controls the general - purpose i/o pins of the adc. table 28 . bit descriptions for gpiocon bits bit name settings description reset access [15:13] reserved these bit s are reserved and should be set to 0. 0x0 r 12 mux_io this bit allows the adc to control an external multiplexer , using gpio0/gpio1 in sync with the internal channel sequencing. the analog input pins used for a channel can still be selected on a per channel basis. therefore, it is possible to have a 4 - channel multiplexer in front of ain0/ain1 and another in front of ain2/ain3, giving a total of eight differential channels with the ad7175 - 2. however, only four channels at a time can b e automatically sequenced. a delay can be inserted after switching an external multiplexer (see the delay bits in the adc mode register ). 0x0 rw 11 sync_en this bit enables the sync / error pin as a sync input. when set low, the sync / error pin holds the adc and filter in reset until sync / error goes high. an alternative operation of the sync / error pin is available when the alt_sync bit in the interface mode register is set. this mode only works when multiple channels are e nabled. in this case, a low on the sync / error pin does not immediately reset the filter/modulator. instead, if the sync / error pin is low when the channel is due to be switched, the modulator and filter are prevented from starting a new conversion. bringing sync / error high begins the next conversion. this alternative sync mode allows sync / error to be used while cycling through channels. 0x1 rw 0 disabled 1 enabled [10:9] err_en these bits enable the sync / error pin as an error input/output. 0x0 rw 00 disabled 01 sync / error is an error input. the (inverted) readback state is or'ed with other error sources and is available in the adc_error bit in the status register. the sync / err or pin state can also be read from the err_dat bit in this register. 10 sync / error is an open - drain error output. the status register error bits are or'ed, inverted, and mapped to the sync / error pin. sync / error pins of multiple devices can be wired together to a common pull - up resistor so that an error on any device can be observed. 11 sync / error is a general - purpose output. the status of the pin is controlled by the err_dat bit in this register. this is referenced between iovdd and dgnd, as opposed to the avdd1 and avss levels used by the general - purpose i/o pins. it has an active pull - up in this case. 8 err_dat this bit determines the logic level at the error pin if the pin is enabled as a general - purpose output. it reflects the readback status of the pin if the pin is enabled as an input. 0x0 rw [7:6] reserved these bit s are reserved and should be set to 0. 0x0 r 5 ip_en1 this bit turns gpio1 into an input. input should equal avdd5 or avss. 0x0 rw 0 disabled 1 enabled 4 ip_en0 this bit turns gpio0 into an input. input should equal avdd5 or avss. 0x0 rw 0 disabled 1 enabled 3 op_en1 this bit turns gpio1 into an output. outputs are referenced between avdd1 and avss. 0x0 rw 0 disabled 1 enabled 2 op_en0 this bit turns gpio0 into an output. outputs are referenced between avdd1 and avss. 0x0 rw
ad7176- 2 data sheet rev. 0 | page 52 of 68 bits bit name settings description reset access 0 disabled 1 enabled 1 gp_data1 this bit is the readback or write data for gpio1. 0x0 rw 0 gp_data0 this bit is the readback or write data for gpio0. 0x0 rw id register address: 0x07, reset: 0x0c9x, name: id the id register returns a 16 - bit id. for the ad7176 - 2 , this should be 0x0c94. table 29 . bit descriptions for id bits bit name settings description reset access [15:0] id the id register returns a 16 - bit id code that is specific to the adc. 0x0c9x r 0x0c9x ad7176 - 2
data sheet ad7176- 2 rev. 0 | page 53 of 68 channel map register 0 address: 0x10, reset: 0x8001, name: chmap0 the channel map registers are 16 - bit registers that are used to select which channels are currently active, which inputs are selected for each channel, and which setup should be used to configure the adc for that channel. table 30 . bit descriptions for chmap0 bits bit name settings description reset access 15 ch_en0 this bit enables channel 0. if more than one channel is enabled, the adc will automatically sequence between them. 0x1 rw 0 disabled 1 enabled (default) 14 reserved this bit is reserved and should be set to 0. 0x0 r [13:12] setup_sel0 these bits identify which of the four setups are used to configure the adc for this channel. a setup comprises a set of four registers: setup configuration register, filter configuration register, offset register, gain register. all channels can use the same setup, in which case the same 3 - bit value should be written to these bits on all active channels, or up to four channels can be configured differently. 0x0 rw 000 setup 0 001 setup 1 010 setup 2 011 setup 3 [11:10] reserved these bit s are reserved and should be set to 0. 0x0 r [9:5] ainpos0 these bits select which of the analog inputs is connected to the positive input of the adc for this channel. 0x0 rw 00000 ain0 (default) 00001 ain1 00010 ain2 00011 ain3 00100 ain4 10101 ref + 10110 ref ? [4:0] ainneg0 these bits select which of the analog inputs is connected to the negative input of the adc for this channel. 0x1 rw 00000 ain0 00001 ain1 (default) 00010 ain2 00011 ain3 00100 ain4 10101 ref + 10110 ref ?
ad7176- 2 data sheet rev. 0 | page 54 of 68 channel map register 1 address: 0x11, reset: 0x0001, name: chmap1 the channel map registers are 16 - bit registers that are used to select which channels are currently active, which inputs are selected for each channel, and which setup should be used to configure the adc for that channel. table 31 . bit de scriptions for chmap1 bits bit name settings description reset access 15 ch_en1 this bit enables channel 1. if more than one channel is enabled, the adc will automatically sequence between them. 0x0 rw 0 disabled (default) 1 enabled 14 reserved this bit is reserved and should be set to 0. 0x0 r [13:12] setup_sel1 these bits identify which of the four setups are used to configure the adc for this channel. a setup comprises a set of four registers: setup configuration register, filter c onfiguration register, offset register, gain register. all channels can use the same setup, in which case the same 3 - bit value should be written to these bits on all active channels, or up to four channels can be configured differently. 0x0 rw 000 setup 0 001 setup 1 010 setup 2 011 setup 3 [11:10] reserved these bit s are reserved and should be set to 0. 0x0 r [9:5] ainpos1 these bits select which of the analog inputs is connected to the positive input of the adc for this channel. 0x0 rw 00000 ain0 (default) 00001 ain1 00010 ain2 00011 ain3 00100 ain4 10101 ref + 10110 ref ? [4:0] ainneg1 these bits select which of the analog inputs is connected to the negative input of the adc for this channel. 0x1 rw 00000 ain0 00001 ain1 (default) 00010 ain2 00011 ain3 00100 ain4 10101 ref + 10110 ref ?
data sheet ad7176- 2 rev. 0 | page 55 of 68 channel map register 2 address: 0x12, reset: 0x0001, name: chmap2 the channel map registers are 16 - bit registers that are used to select which channels are currently active, which inputs are selected for each channel, and which setup should be used to configure the adc for that channel. table 32 . bit descriptions for chmap2 bits bit name settings descrip tion reset access 15 ch_en2 this bit enables channel 2. if more than one channel is enabled, the adc will automatically sequence between them. 0x0 rw 0 disabled (default) 1 enabled 14 reserved this bit is reserved and should be set to 0. 0x0 r [13:12] setup_sel2 these bits identify which of the four setups are used to configure the adc for this channel. a setup comprises a set of four registers: setup configuration register, filter configuration register, offset register, gain register. all channels can use the same setup, in which case the same 3 - bit value should be written to these bits on all active channels, or up to four channels can be configured differently. 0x0 rw 000 setup 0 001 setup 1 010 setup 2 011 setup 3 [11:10] reserved these bit s are reserved and should be set to 0. 0x0 r [9:5] ainpos2 these bits select which of the analog inputs is connected to the positive input of the adc for this channel. 0x0 rw 00000 ain0 (default) 00001 ain1 00010 ain2 00011 ain3 00100 ain4 10101 ref + 10110 ref ? [4:0] ainneg2 these bits select which of the analog inputs is connected to the negative input of the adc for this channel. 0x1 rw 00000 ain0 00001 ain1 (default) 00010 ain2 00011 ain3 00100 ain4 10101 ref + 10110 ref ?
ad7176- 2 data sheet rev. 0 | page 56 of 68 channel map register 3 address: 0x13, reset: 0x0001, name: chmap3 the channel map registers are 16 - bit registers that are used to select which channels are currently active, which inputs are selected for each channel, and which setup should be used to configure the adc for that channel. table 33 . bit descriptions for chmap3 bits bit name settings description reset access 15 ch_en3 this bit enables channel 3. if more than one channel is enabled, the adc will automatically sequence between them. 0x0 rw 0 disabled (default) 1 enabled 14 reserved this bit is reserved and should be set to 0. 0x0 r [13:12] setup_sel3 these bits identify which of the four setups are used to configure the adc for this channel. a setup comprises a set of four registers: setup configuration register, filter configuration register, offset register, gain register. all channels can use the sa me setup, in which case the same 3 - bit value should be written to these bits on all active channels, or up to four channels can be configured differently. 0x0 rw 000 setup 0 001 setup 1 010 setup 2 011 setup 3 [11:10] reserved these bit s are reserved and should be set to 0. 0x0 r [9:5] ainpos3 these bits select which of the analog inputs is connected to the positive input of the adc for this channel. 0x0 rw 00000 ain0 (default) 00001 ain1 00010 ain2 00011 ain3 00100 ain4 10101 ref + 10110 ref ? [4:0] ainneg3 these bits select which of the analog inputs is connected to the negative input of the adc for this channel. 0x1 rw 00000 ain0 00001 ain1 (default) 00010 ain2 00011 ain3 00100 ain4 10101 ref + 10110 ref ?
data sheet ad7176- 2 rev. 0 | page 57 of 68 setup configuration register 0 address: 0x20, reset: 0x1020, name: setupcon0 the setup configuration registers are 16 - bit registers that configure the reference selection and output coding of the adc. table 34 . bit descriptions for setupcon0 bits bit name settings description reset access [15:13] reserved these bit s are reserved and should be set to 0. 0x0 r 12 bi_unipolar0 this bit sets the output coding of the adc for setup 0. 0x1 rw 0 unipolar coded output 1 offset binary coded output [11:6] reserved these bit s are reserved and should be set to 0. 0x00 r [5:4] ref_sel0 these bits allow you to select the reference source for adc conversion on setup 0. 0x2 rw 00 external reference. 10 internal 2.5 v reference. this must also be enabled in the adc mode register. 11 avdd1 ? avss. this can be used to as a diagnostic to validate other reference values. [3:0] reserved these bit s are reserved and should be set to 0. 0x0 r setup configuration register 1 address: 0x21, reset: 0x1020, name: setupcon1 the setup configuration registers are 16 - bit registers that configure the reference selection and output coding of the adc. table 35 . bit descriptions for setupcon1 bits bit name settings description reset access [15:13] reserved these bit s are reserved and should be set to 0. 0x0 r 12 bi_unipolar1 this bit sets the output coding of the adc for setup 1. 0x1 rw 0 unipolar coded output 1 offset binary coded output [11:6] reserved these bit s are reserved and should be set to 0. 0x00 r [5:4] ref_sel1 these bits allow you to select the reference source for adc conversion on setup 1. 0x2 rw 00 external reference 10 internal 2.5 v reference. this must also be enabled in the adc mode register. 11 avdd1 ? avss. this can be used to as a diagnostic to validate other reference values. [3:0] reserved these bit s are reserved and should be set to 0. 0x0 r
ad7176- 2 data sheet rev. 0 | page 58 of 68 setup configuration register 2 address: 0x22, reset: 0x1020, name: setupcon2 the setup configuration registers are 16 - bit registers that configure the reference selection and output coding of the adc. table 36. bit descriptions for setupcon2 bits bit name settings description reset access [15:13] reserved these bit s are reserved and should be set to 0. 0x0 r 12 bi_unipolar2 this bit sets the output coding of the adc for setup 2. 0x1 rw 0 unipolar coded output 1 offset binary coded output [11:6] reserved these bit s are reserved and should be set to 0. 0x00 r [5:4] ref_sel2 these bits allow you to select the reference source for adc conversion on setup 2. 0x2 rw 00 external reference 10 internal 2.5 v reference. this must also be enabled in the adc mode register. 11 avdd1 ? avss. this can be used to as a diagnostic to validate other reference values. [3:0] reserved these bit s are reserved and should be set to 0. 0x0 r setup configuration register 3 address: 0x23, reset: 0x1020, name: setupcon3 the setup configuration registers are 16 - bit registers that configure the reference selection and output coding of the adc. table 37. bit descriptions for setupcon3 bits bit name settings description reset access [15:13] reserved these bit s are reserved and should be set to 0. 0x0 r 12 bi_unipolar3 this bit sets the output coding of the adc for setup 3. 0x1 rw 0 unipolar coded output 1 offset binary coded output [11:6] reserved these bit s are reserved and should be set to 0. 0x00 r [5:4] ref_sel3 these bits allow you to select the reference source for adc conversion on setup 3. 0x2 rw 00 external reference 10 internal 2.5 v reference. this must also be enabled in the adc mode register. 11 avdd1 ? avss. this can be used to as a diagnostic to validate other reference values. [3:0] reserved these bit s are reserved and should be set to 0. 0x0 r
data sheet ad7176- 2 rev. 0 | page 59 of 68 filter configuration register 0 address: 0x28, reset: 0x0000, name: filtcon0 the filter configuration registers are 16 - bit registers that configure the adc data rate and filter options. writing to any of these registers resets any active adc conversion and restarts converting at the first channel in the sequence. table 38 . bit descriptions for filtcon0 bits bit name settings description reset access 15 sinc3_map0 if this bit is set, the mapping of the filter register changes to directly program the decimation rate of the sinc3 filter for setup 0. all other options are eliminated. this allows for fine tuning of the output data rate and filter notch for rejection of specific frequencies. the data rate when on a single channel equals fmod/(32 filtcon0[14:0]). 0x0 rw [14:12] reserved these bit s are reserved and should be set to 0. 0x0 r 11 enhfilten0 this bit enables various post filters for enhanced 50 hz/60 hz rejection for setup 0. the order bits must be set to 00 to select the sinc5 + sinc1 filter for this to work. 0x0 rw 0 disabled 1 enabled [10:8] enhfilt0 these bits select between various post filters for enhanced 50 hz/60 hz rejection for setup 0. 0x0 rw 010 27 sps, 47 db rejection, 36.7 ms settling 011 25 sps, 62 db rejection, 40 ms settling 101 20 sps, 86 db rejection, 50 ms settling 110 16.67 sps, 92 db rejection, 60 ms settling 7 reserved this bit is reserved and should be set to 0. 0x0 r [6:5] order0 these bits control the order of the digital filter that processes the modulator data for setup 0. 0x0 rw 00 sinc5 + sinc1 (default) 11 sinc3 [4:0] odr0 these bits control the output data rate of the adc and, therefore, the settling time and noise for setup 0. 0x0 rw 00000 250,000 00001 125,000 00010 62,500 00011 50,000 00100 31,250 00101 25,000 00110 15,625 00111 10,000 01000 5000 01001 2500 01010 1000 01011 500 01100 397.5 01101 200 01110 100 01111 59.94 10000 49.96 10001 20 10010 16.667 10011 10 10100 5
ad7176- 2 data sheet rev. 0 | page 60 of 68 filter configuration register 1 address: 0x29, reset: 0x0000, name: filtcon1 the filter configuration registers are 16 - bit registers that configure the adc data rate and filter options. writing to any of these registers resets any active adc conversion and restarts converting at the first channel in the sequence. table 39 . bit descrip tions for filtcon1 bits bit name settings description reset access 15 sinc3_map1 if this bit is set, the mapping of the filter register changes to directly program the decimation rate of the sinc3 filter for setup 1. all other options are eliminated . this allows for fine tuning of the output data rate and filter notch for rejection of specific frequencies. the data rate when on a single channel equals fmod/(32 filtcon1[14:0]). 0x0 rw [14:12] reserved these bit s are reserved and should be set to 0. 0x0 r 11 enhfilten1 this bit enables various post filters for enhanced 50 hz/60 hz rejection for setup 1. the order bits must be set to 00 to select the sinc5 + sinc1 filter for this to work. 0x0 rw 0 disabled 1 enabled [10:8] enhfilt1 these bits select between various post filters for enhanced 50 hz/60 hz rejection for setup 1. 0x0 rw 010 27 sps, 47 db rejection, 36.7 ms settling 011 25 sps, 62 db rejection, 40 ms settling 101 20 sps, 86 db rejection, 50 ms settling 110 16.67 sps, 92 db rejection, 60 ms settling 7 reserved this bit is reserved and should be set to 0. 0x0 r [6:5] order1 these bits control the order of the digital filter that processes the modulator data for setup 1. 0x0 rw 00 sinc5 + sinc1 (default) 11 sinc3 [4:0] odr1 these bits control the output data rate of the adc and, therefore, the settling time and noise for setup 1. 0x0 rw 00000 250,000 00001 125,000 00010 62,500 00011 50,000 00100 31,250 00101 25,000 00110 15,625 00111 10,000 01000 5000 01001 2500 01010 1000 01011 500 01100 397.5 01101 200 01110 100 01111 59.94 10000 49.96 10001 20 10010 16.667 10011 10 10100 5
data sheet ad7176- 2 rev. 0 | page 61 of 68 filter configuration register 2 address: 0x2a, reset: 0x0000, name: filtcon2 the filter configuration registers are 16 - bit registers that configure the adc data rate and filter options. writing to any of these registers resets any active adc conversion and restarts converting at the first channel in the sequence. table 40 . bit descriptions for filtcon2 bits bit name settings description reset access 15 sinc3_map2 if this bit is set, the mapping of the filter register changes to directly program the decimation rate of the sinc3 filter for setup 2. all other options are eliminated. this allows for fine tuning of the output data rate and filter notch for rejection of specific frequencies. the data rate when on a single channel equals fmod/(32 filtcon2[14:0]). 0x0 rw [14:12] reserved these bit s are reserved and should be set to 0. 0x0 r 11 enhfilten2 this bit enables various post filters for enhanced 50 hz/60 hz rejection for setup 2. the order bits must be set to 00 to select the sinc5 + sinc1 filter for this to work. 0x0 rw 0 disabled 1 enabled [10:8] enhfilt2 these bits select between various post filters for enhanced 50 hz/60 hz rejection for setup 2. 0x0 rw 010 27 sps, 47db rejection, 36.7 ms settling 011 25 sps, 62 db rejection, 40 ms settling 101 20 sps, 86 db rejection, 50 ms settling 110 16.67 sps, 92 db rejection, 60 ms settling 7 reserved this bit is reserved and should be set to 0. 0x0 r [6:5] order2 these bits control the order of the digital filter that processes the modulator data for setup 2. 0x0 rw 00 sinc5 + sinc1 (default) 11 sinc3 [4:0] odr2 these bits control the output data rate of the adc and, therefore, the settling time and noise for setup 2. 0x0 rw 00000 250,000 00001 125,000 00010 62,500 00011 50,000 00100 31,250 00101 25,000 00110 15,625 00111 10,000 01000 5000 01001 2500 01010 1000 01011 500 01100 397.5 01101 200 01110 100 01111 59.94 10000 49.96 10001 20 10010 16.667 10011 10 10100 5
ad7176- 2 data sheet rev. 0 | page 62 of 68 filter configuration register 3 address: 0x2b, reset: 0x0000, name: filtcon3 the filter configuration registers are 16 - bit registers that configure the adc data rate and filter options. writing to any of these registers resets any active adc conversion and restarts converting at the first channel in the sequence. table 41 . bit descrip tions for filtcon3 bits bit name settings description reset access 15 sinc3_map3 if this bit is set, the mapping of the filter register changes to directly program the decimation rate of the sinc3 filter for setup 3. all other options are eliminated . this allows for fine tuning of the output data rate and filter notch for rejection of specific frequencies. the data rate when on a single channel equals fmod/(32 filtcon3[14:0]). 0x0 rw [14:12] reserved these bit s are reserved and should be set to 0. 0x0 r 11 enhfilten3 this bit enables various post filters for enhanced 50 hz/60 hz rejection for setup 3. the order bits must be set to 00 to select the sinc5 + sinc1 filter for this to work. 0x0 rw 0 disabled 1 enabled [10:8] enhfilt3 these bits select between various post filters for enhanced 50 hz/60 hz rejection for setup 3. 0x0 rw 010 27 sps, 47 db rejection, 36.7 ms settling 011 25 sps, 62 db rejection, 40 ms settling 101 20 sps, 86 db rejection, 50 ms settling 110 16.67 sps, 92 db rejection, 60 ms settling 7 reserved this bit is reserved and should be set to 0. 0x0 r [6:5] order3 these bits control the order of the digital filter that processes the modulator data for setup 3. 0x0 rw 00 sinc5 + sinc1 (default) 11 sinc3 [4:0] odr3 these bits control the output data rate of the adc and, therefore, the settling time and noise for setup 3. 0x0 rw 00000 250,000 00001 125,000 00010 62,500 00011 50,000 00100 31,250 00101 25,000 00110 15,625 00111 10,000 01000 5000 01001 2500 01010 1000 01011 500 01100 397.5 01101 200 01110 100 01111 59.94 10000 49.96 10001 20 10010 16.667 10011 10 10100 5
data sheet ad7176- 2 rev. 0 | page 63 of 68 offset register 0 address: 0x30, reset: 0x800000, name: offset0 the offset (zero - scale) registers are 24 - bit registers that can be used to compensate for any offset error in the adc or in the system. table 42. bit descriptions for offset0 bits bit name settings description reset access [23:0] offset0 offset calibration coefficient for setup 0. 0x800000 rw offset register 1 address: 0x31, reset: 0x800000, name: offset1 the offset (zero - scale) registers are 24 - bit registers that can be used to compensate for any offset error in the adc or in the system. table 43 . bit descriptions for offset1 bits bit name settings description reset access [23:0] offset1 offset calibration coefficient for setup 1. 0x800000 rw offset register 2 address: 0x32, reset: 0x800000, name: offset2 the offset (zero - scale) registers are 24 - bit registers that can be used to compensate for any offset error in the adc or in the system. table 44 . bit descriptions for offset2 bits bit name settings description reset access [23:0] offset2 offset calibration coefficient for setup 2. 0x800000 rw offset register 3 address: 0x33, reset: 0x800000, name: offset3 the offset (zero - scale) registers are 24 - bit registers that can be used to compensate for any offset error in the adc or in the system. table 45 . bit descriptions for offset3 bi ts bit name settings description reset access [23:0] offset3 offset calibration coefficient for setup 3. 0x800000 rw
ad7176- 2 data sheet rev. 0 | page 64 of 68 gain register 0 address: 0x38, reset: 0x5xxxx0, name: gain0 the gain (full - scale) registers are 24 - bit registers that can be used to compensate for any gain error in the adc or in the system. table 46 . bit descriptions for gain0 bits bit name settings description reset access [23:0] gain0 gain calibration coefficient for setup 0. 0x5xxxx0 rw gain register 1 address: 0x39, reset: 0x5xxxx0, name: gain1 the gain (full - scale) registers are 24 - bit registers that can be used to compensate for any gain error in the adc or in the system. table 47 . bit descriptions for gain1 bits bit name settin gs description reset access [23:0] gain1 gain calibration coefficient for setup 1. 0x5xxxx0 rw gain register 2 address: 0x3a, reset: 0x5xxxx0, name: gain2 the gain (full - scale) registers are 24 - bit registers that can be used to compensate for any gain error in the adc or in the system. table 48 . bit descriptions for gain2 bits bit name settings description reset access [23:0] gain2 gain calibration coefficient for setup 2. 0x5xxxx0 rw gain register 3 address: 0x3b, reset: 0x5xxxx0, name: gain3 the gain (full - scale) registers are 24 - bit registers that can be used to compensate for any gain error in the adc or in the system. table 49 . bit descriptions for gain3 bits bit name settin gs description reset access [23:0] gain3 gain calibration coefficient for setup 3. 0x5xxxx0 rw
data sheet ad7176- 2 rev. 0 | page 65 of 68 outline dimensions figure 52 . 24 - lead thin shrink small outline package [tssop] (ru - 24) dimensions shown in millimeters ordering guide models 1 temperature range package description package option ad717 6 -2 bruz C 40c to +105c 24- lead tssop ru -24 ad717 6 -2 bruz - rl C 40c to +105c 24- lead tssop ru -24 eval - ad7176- 2sdz evaluation board eval - sdp - cb1z evaluation controller board 1 z = rohs compliant part. 24 13 12 1 6.40 bsc 4.50 4.40 4.30 pin 1 7.90 7.80 7.70 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 seating plane 0.10 coplanarity compliant to jedec standards mo-153-ad
ad7176- 2 data sheet rev. 0 | page 66 of 68 notes
data sheet ad7176- 2 rev. 0 | page 67 of 68 notes
ad7176- 2 data sheet rev. 0 | page 68 of 68 notes ? 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d11037 - 0- 11/12(0)

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